[ECP5] Missing pip on GUI?

[krisdamk]

I synthesized the following circuit (an AND gate) with Yosys:

module test(input btn1, input btn2, output led); 
	
	wire lut_output;
	
	LUT4 #(.INIT(16'h8000)) lut(btn1, btn2, 1'b1, 1'b1, lut_output);
	
	assign led = lut_output;
endmodule

I loaded the module’s json file to nextpnr, along with the following lpf file:

LOCATE COMP "led" SITE "B2";
IOBUF  PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;

LOCATE COMP "btn1" SITE "R1";
IOBUF  PORT "btn1" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;

LOCATE COMP "btn2" SITE "T1";
IOBUF  PORT "btn2" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;

After pack, place, route, and enabling pip drawing, close to the leftmost top IO pad, I see the following:

(Dumb question: The square in the middle of the viewport is a switchbox, right? Just to be sure.)

The ROUTING attribute of the selected net contains the following:

X4/Y95/JPADDIB_PIO;;
1;
X4/Y95/JDIB;
X4/Y95/0_0_JPADDIB_PIO->0_0_JDIB;
1;
X5/Y94/JQ0;
X4/Y95/0_0_JDIB->1_-1_JQ0;
1;
X5/Y94/H01W0000;
X5/Y94/0_0_JQ0->0_0_H01W0000;
1;
X4/Y93/V02N0401;
X4/Y94/1_0_H01W0000->0_-1_V02N0401;
1;
X4/Y93/D5;
X4/Y93/0_0_V02N0401->0_0_D5;
1;
X4/Y93/B5_SLICE;
X4/Y93/0_0_D5->0_0_B5_SLICE;1

It seems like a pip is missing on the viewport between the wires X5/Y94/JQ0 and X5/Y94/H01W0000.

I guess this is a bug? The design works fine on an ULX3S, so I don’t think this causes problems with the bitstream.

(nextpnr version: 0.9-19-g4b00f58a, built with using UCRT64 MSYS2 packages - not sure the latter is relevant)