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wangpc-ppwangpc-pp
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Update tests
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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,15 @@ body: |
1111
bb.0.entry:
1212
; RV32I-LABEL: name: select_nxv1i8
1313
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
14-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
14+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
1515
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
1616
; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */
1717
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
1818
; RV32I-NEXT: PseudoRET implicit $v8
1919
;
2020
; RV64I-LABEL: name: select_nxv1i8
2121
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
22-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
22+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
2323
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
2424
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */
2525
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
@@ -40,15 +40,15 @@ body: |
4040
bb.0.entry:
4141
; RV32I-LABEL: name: select_nxv4i8
4242
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
43-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
43+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
4444
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
4545
; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */
4646
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
4747
; RV32I-NEXT: PseudoRET implicit $v8
4848
;
4949
; RV64I-LABEL: name: select_nxv4i8
5050
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
51-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
51+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
5252
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
5353
; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */
5454
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
@@ -69,15 +69,15 @@ body: |
6969
bb.0.entry:
7070
; RV32I-LABEL: name: select_nxv16i8
7171
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
72-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
72+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
7373
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
7474
; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */
7575
; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
7676
; RV32I-NEXT: PseudoRET implicit $v8m4
7777
;
7878
; RV64I-LABEL: name: select_nxv16i8
7979
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
80-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
80+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
8181
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
8282
; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */
8383
; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
@@ -98,15 +98,15 @@ body: |
9898
bb.0.entry:
9999
; RV32I-LABEL: name: select_nxv64i8
100100
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
101-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
101+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
102102
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
103103
; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */
104104
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
105105
; RV32I-NEXT: PseudoRET implicit $v8
106106
;
107107
; RV64I-LABEL: name: select_nxv64i8
108108
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
109-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
109+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
110110
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
111111
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */
112112
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
@@ -127,15 +127,15 @@ body: |
127127
bb.0.entry:
128128
; RV32I-LABEL: name: select_nxv2i16
129129
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
130-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
130+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
131131
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
132132
; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */
133133
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
134134
; RV32I-NEXT: PseudoRET implicit $v8
135135
;
136136
; RV64I-LABEL: name: select_nxv2i16
137137
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
138-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
138+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
139139
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
140140
; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */
141141
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
@@ -156,15 +156,15 @@ body: |
156156
bb.0.entry:
157157
; RV32I-LABEL: name: select_nxv8i16
158158
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
159-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
159+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
160160
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
161161
; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */
162162
; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
163163
; RV32I-NEXT: PseudoRET implicit $v8m4
164164
;
165165
; RV64I-LABEL: name: select_nxv8i16
166166
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
167-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
167+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
168168
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
169169
; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */
170170
; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
@@ -185,15 +185,15 @@ body: |
185185
bb.0.entry:
186186
; RV32I-LABEL: name: select_nxv32i16
187187
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
188-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
188+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
189189
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
190190
; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */
191191
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]
192192
; RV32I-NEXT: PseudoRET implicit $v8
193193
;
194194
; RV64I-LABEL: name: select_nxv32i16
195195
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
196-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
196+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
197197
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
198198
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */
199199
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]
@@ -214,15 +214,15 @@ body: |
214214
bb.0.entry:
215215
; RV32I-LABEL: name: select_nxv2i32
216216
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
217-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
217+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
218218
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
219219
; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */
220220
; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
221221
; RV32I-NEXT: PseudoRET implicit $v8m2
222222
;
223223
; RV64I-LABEL: name: select_nxv2i32
224224
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
225-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
225+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
226226
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
227227
; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */
228228
; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
@@ -243,15 +243,15 @@ body: |
243243
bb.0.entry:
244244
; RV32I-LABEL: name: select_nxv8i32
245245
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
246-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
246+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
247247
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
248248
; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */
249249
; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
250250
; RV32I-NEXT: PseudoRET implicit $v8m8
251251
;
252252
; RV64I-LABEL: name: select_nxv8i32
253253
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
254-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
254+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
255255
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
256256
; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */
257257
; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
@@ -272,15 +272,15 @@ body: |
272272
bb.0.entry:
273273
; RV32I-LABEL: name: select_nxv1i64
274274
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
275-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
275+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
276276
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
277277
; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */
278278
; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
279279
; RV32I-NEXT: PseudoRET implicit $v8m2
280280
;
281281
; RV64I-LABEL: name: select_nxv1i64
282282
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
283-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
283+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
284284
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
285285
; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */
286286
; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
@@ -301,15 +301,15 @@ body: |
301301
bb.0.entry:
302302
; RV32I-LABEL: name: select_nxv4i64
303303
; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
304-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
304+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
305305
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
306306
; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */
307307
; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
308308
; RV32I-NEXT: PseudoRET implicit $v8m8
309309
;
310310
; RV64I-LABEL: name: select_nxv4i64
311311
; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF
312-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
312+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
313313
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
314314
; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */
315315
; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]

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