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Wolfram70Wolfram70
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remove mixed precision intrinsics and use idioms
1 parent 444a0a7 commit 9b02a28

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8 files changed

+465
-464
lines changed

8 files changed

+465
-464
lines changed

‎clang/include/clang/Basic/BuiltinsNVPTX.td‎

Lines changed: 37 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -389,36 +389,26 @@ def __nvvm_fma_rn_relu_bf16 : NVPTXBuiltinSMAndPTX<"__bf16(__bf16, __bf16, __bf1
389389
def __nvvm_fma_rn_bf16x2 : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(_Vector<2, __bf16>, _Vector<2, __bf16>, _Vector<2, __bf16>)", SM_80, PTX70>;
390390
def __nvvm_fma_rn_relu_bf16x2 : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(_Vector<2, __bf16>, _Vector<2, __bf16>, _Vector<2, __bf16>)", SM_80, PTX70>;
391391
def __nvvm_fma_rn_ftz_f : NVPTXBuiltin<"float(float, float, float)">;
392+
def __nvvm_fma_rn_ftz_sat_f : NVPTXBuiltin<"float(float, float, float)">;
392393
def __nvvm_fma_rn_f : NVPTXBuiltin<"float(float, float, float)">;
394+
def __nvvm_fma_rn_sat_f : NVPTXBuiltin<"float(float, float, float)">;
393395
def __nvvm_fma_rz_ftz_f : NVPTXBuiltin<"float(float, float, float)">;
396+
def __nvvm_fma_rz_ftz_sat_f : NVPTXBuiltin<"float(float, float, float)">;
394397
def __nvvm_fma_rz_f : NVPTXBuiltin<"float(float, float, float)">;
398+
def __nvvm_fma_rz_sat_f : NVPTXBuiltin<"float(float, float, float)">;
395399
def __nvvm_fma_rm_ftz_f : NVPTXBuiltin<"float(float, float, float)">;
400+
def __nvvm_fma_rm_ftz_sat_f : NVPTXBuiltin<"float(float, float, float)">;
396401
def __nvvm_fma_rm_f : NVPTXBuiltin<"float(float, float, float)">;
402+
def __nvvm_fma_rm_sat_f : NVPTXBuiltin<"float(float, float, float)">;
397403
def __nvvm_fma_rp_ftz_f : NVPTXBuiltin<"float(float, float, float)">;
404+
def __nvvm_fma_rp_ftz_sat_f : NVPTXBuiltin<"float(float, float, float)">;
398405
def __nvvm_fma_rp_f : NVPTXBuiltin<"float(float, float, float)">;
406+
def __nvvm_fma_rp_sat_f : NVPTXBuiltin<"float(float, float, float)">;
399407
def __nvvm_fma_rn_d : NVPTXBuiltin<"double(double, double, double)">;
400408
def __nvvm_fma_rz_d : NVPTXBuiltin<"double(double, double, double)">;
401409
def __nvvm_fma_rm_d : NVPTXBuiltin<"double(double, double, double)">;
402410
def __nvvm_fma_rp_d : NVPTXBuiltin<"double(double, double, double)">;
403411

404-
def __nvvm_fma_mixed_rn_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
405-
def __nvvm_fma_mixed_rz_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
406-
def __nvvm_fma_mixed_rm_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
407-
def __nvvm_fma_mixed_rp_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
408-
def __nvvm_fma_mixed_rn_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
409-
def __nvvm_fma_mixed_rz_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
410-
def __nvvm_fma_mixed_rm_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
411-
def __nvvm_fma_mixed_rp_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, __fp16, float)", SM_100, PTX86>;
412-
413-
def __nvvm_fma_mixed_rn_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
414-
def __nvvm_fma_mixed_rz_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
415-
def __nvvm_fma_mixed_rm_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
416-
def __nvvm_fma_mixed_rp_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
417-
def __nvvm_fma_mixed_rn_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
418-
def __nvvm_fma_mixed_rz_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
419-
def __nvvm_fma_mixed_rm_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
420-
def __nvvm_fma_mixed_rp_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, __bf16, float)", SM_100, PTX86>;
421-
422412
// Rcp
423413

424414
def __nvvm_rcp_rn_ftz_f : NVPTXBuiltin<"float(float)">;
@@ -465,64 +455,50 @@ def __nvvm_rsqrt_approx_d : NVPTXBuiltin<"double(double)">;
465455
// Add
466456

467457
def __nvvm_add_rn_ftz_f : NVPTXBuiltin<"float(float, float)">;
458+
def __nvvm_add_rn_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
468459
def __nvvm_add_rn_f : NVPTXBuiltin<"float(float, float)">;
460+
def __nvvm_add_rn_sat_f : NVPTXBuiltin<"float(float, float)">;
469461
def __nvvm_add_rz_ftz_f : NVPTXBuiltin<"float(float, float)">;
462+
def __nvvm_add_rz_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
470463
def __nvvm_add_rz_f : NVPTXBuiltin<"float(float, float)">;
464+
def __nvvm_add_rz_sat_f : NVPTXBuiltin<"float(float, float)">;
471465
def __nvvm_add_rm_ftz_f : NVPTXBuiltin<"float(float, float)">;
466+
def __nvvm_add_rm_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
472467
def __nvvm_add_rm_f : NVPTXBuiltin<"float(float, float)">;
468+
def __nvvm_add_rm_sat_f : NVPTXBuiltin<"float(float, float)">;
473469
def __nvvm_add_rp_ftz_f : NVPTXBuiltin<"float(float, float)">;
470+
def __nvvm_add_rp_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
474471
def __nvvm_add_rp_f : NVPTXBuiltin<"float(float, float)">;
472+
def __nvvm_add_rp_sat_f : NVPTXBuiltin<"float(float, float)">;
475473

476474
def __nvvm_add_rn_d : NVPTXBuiltin<"double(double, double)">;
477475
def __nvvm_add_rz_d : NVPTXBuiltin<"double(double, double)">;
478476
def __nvvm_add_rm_d : NVPTXBuiltin<"double(double, double)">;
479477
def __nvvm_add_rp_d : NVPTXBuiltin<"double(double, double)">;
480478

481-
def __nvvm_add_mixed_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
482-
def __nvvm_add_mixed_rn_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
483-
def __nvvm_add_mixed_rz_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
484-
def __nvvm_add_mixed_rm_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
485-
def __nvvm_add_mixed_rp_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
486-
def __nvvm_add_mixed_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
487-
def __nvvm_add_mixed_rn_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
488-
def __nvvm_add_mixed_rz_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
489-
def __nvvm_add_mixed_rm_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
490-
def __nvvm_add_mixed_rp_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
491-
492-
def __nvvm_add_mixed_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
493-
def __nvvm_add_mixed_rn_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
494-
def __nvvm_add_mixed_rz_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
495-
def __nvvm_add_mixed_rm_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
496-
def __nvvm_add_mixed_rp_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
497-
def __nvvm_add_mixed_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
498-
def __nvvm_add_mixed_rn_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
499-
def __nvvm_add_mixed_rz_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
500-
def __nvvm_add_mixed_rm_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
501-
def __nvvm_add_mixed_rp_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
502-
503479
// Sub
504480

505-
def __nvvm_sub_mixed_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
506-
def __nvvm_sub_mixed_rn_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
507-
def __nvvm_sub_mixed_rz_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
508-
def __nvvm_sub_mixed_rm_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
509-
def __nvvm_sub_mixed_rp_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
510-
def __nvvm_sub_mixed_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
511-
def __nvvm_sub_mixed_rn_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
512-
def __nvvm_sub_mixed_rz_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
513-
def __nvvm_sub_mixed_rm_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
514-
def __nvvm_sub_mixed_rp_sat_f16_f32 : NVPTXBuiltinSMAndPTX<"float(__fp16, float)", SM_100, PTX86>;
515-
516-
def __nvvm_sub_mixed_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
517-
def __nvvm_sub_mixed_rn_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
518-
def __nvvm_sub_mixed_rz_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
519-
def __nvvm_sub_mixed_rm_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
520-
def __nvvm_sub_mixed_rp_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
521-
def __nvvm_sub_mixed_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
522-
def __nvvm_sub_mixed_rn_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
523-
def __nvvm_sub_mixed_rz_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
524-
def __nvvm_sub_mixed_rm_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
525-
def __nvvm_sub_mixed_rp_sat_bf16_f32 : NVPTXBuiltinSMAndPTX<"float(__bf16, float)", SM_100, PTX86>;
481+
def __nvvm_sub_rn_ftz_f : NVPTXBuiltin<"float(float, float)">;
482+
def __nvvm_sub_rn_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
483+
def __nvvm_sub_rn_f : NVPTXBuiltin<"float(float, float)">;
484+
def __nvvm_sub_rn_sat_f : NVPTXBuiltin<"float(float, float)">;
485+
def __nvvm_sub_rz_ftz_f : NVPTXBuiltin<"float(float, float)">;
486+
def __nvvm_sub_rz_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
487+
def __nvvm_sub_rz_f : NVPTXBuiltin<"float(float, float)">;
488+
def __nvvm_sub_rz_sat_f : NVPTXBuiltin<"float(float, float)">;
489+
def __nvvm_sub_rm_ftz_f : NVPTXBuiltin<"float(float, float)">;
490+
def __nvvm_sub_rm_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
491+
def __nvvm_sub_rm_f : NVPTXBuiltin<"float(float, float)">;
492+
def __nvvm_sub_rm_sat_f : NVPTXBuiltin<"float(float, float)">;
493+
def __nvvm_sub_rp_ftz_f : NVPTXBuiltin<"float(float, float)">;
494+
def __nvvm_sub_rp_ftz_sat_f : NVPTXBuiltin<"float(float, float)">;
495+
def __nvvm_sub_rp_f : NVPTXBuiltin<"float(float, float)">;
496+
def __nvvm_sub_rp_sat_f : NVPTXBuiltin<"float(float, float)">;
497+
498+
def __nvvm_sub_rn_d : NVPTXBuiltin<"double(double, double)">;
499+
def __nvvm_sub_rz_d : NVPTXBuiltin<"double(double, double)">;
500+
def __nvvm_sub_rm_d : NVPTXBuiltin<"double(double, double)">;
501+
def __nvvm_sub_rp_d : NVPTXBuiltin<"double(double, double)">;
526502

527503
// Convert
528504

‎clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp‎

Lines changed: 0 additions & 123 deletions
Original file line numberDiff line numberDiff line change
@@ -415,17 +415,6 @@ static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
415415
return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID), BuiltinID, E, CGF);
416416
}
417417

418-
static Value *MakeMixedPrecisionFPArithmetic(unsigned IntrinsicID,
419-
const CallExpr *E,
420-
CodeGenFunction &CGF) {
421-
SmallVector<llvm::Value *, 3> Args;
422-
for (unsigned i = 0; i < E->getNumArgs(); ++i) {
423-
Args.push_back(CGF.EmitScalarExpr(E->getArg(i)));
424-
}
425-
return CGF.Builder.CreateCall(
426-
CGF.CGM.getIntrinsic(IntrinsicID, {Args[0]->getType()}), Args);
427-
}
428-
429418
} // namespace
430419

431420
Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
@@ -1208,118 +1197,6 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
12081197
return Builder.CreateCall(
12091198
CGM.getIntrinsic(Intrinsic::nvvm_barrier_cta_sync_count),
12101199
{EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
1211-
case NVPTX::BI__nvvm_add_mixed_f16_f32:
1212-
case NVPTX::BI__nvvm_add_mixed_bf16_f32:
1213-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_f32, E,
1214-
*this);
1215-
case NVPTX::BI__nvvm_add_mixed_rn_f16_f32:
1216-
case NVPTX::BI__nvvm_add_mixed_rn_bf16_f32:
1217-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rn_f32, E,
1218-
*this);
1219-
case NVPTX::BI__nvvm_add_mixed_rz_f16_f32:
1220-
case NVPTX::BI__nvvm_add_mixed_rz_bf16_f32:
1221-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rz_f32, E,
1222-
*this);
1223-
case NVPTX::BI__nvvm_add_mixed_rm_f16_f32:
1224-
case NVPTX::BI__nvvm_add_mixed_rm_bf16_f32:
1225-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rm_f32, E,
1226-
*this);
1227-
case NVPTX::BI__nvvm_add_mixed_rp_f16_f32:
1228-
case NVPTX::BI__nvvm_add_mixed_rp_bf16_f32:
1229-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rp_f32, E,
1230-
*this);
1231-
case NVPTX::BI__nvvm_add_mixed_sat_f16_f32:
1232-
case NVPTX::BI__nvvm_add_mixed_sat_bf16_f32:
1233-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_sat_f32, E,
1234-
*this);
1235-
case NVPTX::BI__nvvm_add_mixed_rn_sat_f16_f32:
1236-
case NVPTX::BI__nvvm_add_mixed_rn_sat_bf16_f32:
1237-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rn_sat_f32,
1238-
E, *this);
1239-
case NVPTX::BI__nvvm_add_mixed_rz_sat_f16_f32:
1240-
case NVPTX::BI__nvvm_add_mixed_rz_sat_bf16_f32:
1241-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rz_sat_f32,
1242-
E, *this);
1243-
case NVPTX::BI__nvvm_add_mixed_rm_sat_f16_f32:
1244-
case NVPTX::BI__nvvm_add_mixed_rm_sat_bf16_f32:
1245-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rm_sat_f32,
1246-
E, *this);
1247-
case NVPTX::BI__nvvm_add_mixed_rp_sat_f16_f32:
1248-
case NVPTX::BI__nvvm_add_mixed_rp_sat_bf16_f32:
1249-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_add_mixed_rp_sat_f32,
1250-
E, *this);
1251-
case NVPTX::BI__nvvm_sub_mixed_f16_f32:
1252-
case NVPTX::BI__nvvm_sub_mixed_bf16_f32:
1253-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_f32, E,
1254-
*this);
1255-
case NVPTX::BI__nvvm_sub_mixed_rn_f16_f32:
1256-
case NVPTX::BI__nvvm_sub_mixed_rn_bf16_f32:
1257-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rn_f32, E,
1258-
*this);
1259-
case NVPTX::BI__nvvm_sub_mixed_rz_f16_f32:
1260-
case NVPTX::BI__nvvm_sub_mixed_rz_bf16_f32:
1261-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rz_f32, E,
1262-
*this);
1263-
case NVPTX::BI__nvvm_sub_mixed_rm_f16_f32:
1264-
case NVPTX::BI__nvvm_sub_mixed_rm_bf16_f32:
1265-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rm_f32, E,
1266-
*this);
1267-
case NVPTX::BI__nvvm_sub_mixed_rp_f16_f32:
1268-
case NVPTX::BI__nvvm_sub_mixed_rp_bf16_f32:
1269-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rp_f32, E,
1270-
*this);
1271-
case NVPTX::BI__nvvm_sub_mixed_sat_f16_f32:
1272-
case NVPTX::BI__nvvm_sub_mixed_sat_bf16_f32:
1273-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_sat_f32, E,
1274-
*this);
1275-
case NVPTX::BI__nvvm_sub_mixed_rn_sat_f16_f32:
1276-
case NVPTX::BI__nvvm_sub_mixed_rn_sat_bf16_f32:
1277-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rn_sat_f32,
1278-
E, *this);
1279-
case NVPTX::BI__nvvm_sub_mixed_rz_sat_f16_f32:
1280-
case NVPTX::BI__nvvm_sub_mixed_rz_sat_bf16_f32:
1281-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rz_sat_f32,
1282-
E, *this);
1283-
case NVPTX::BI__nvvm_sub_mixed_rm_sat_f16_f32:
1284-
case NVPTX::BI__nvvm_sub_mixed_rm_sat_bf16_f32:
1285-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rm_sat_f32,
1286-
E, *this);
1287-
case NVPTX::BI__nvvm_sub_mixed_rp_sat_f16_f32:
1288-
case NVPTX::BI__nvvm_sub_mixed_rp_sat_bf16_f32:
1289-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_sub_mixed_rp_sat_f32,
1290-
E, *this);
1291-
case NVPTX::BI__nvvm_fma_mixed_rn_f16_f32:
1292-
case NVPTX::BI__nvvm_fma_mixed_rn_bf16_f32:
1293-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rn_f32, E,
1294-
*this);
1295-
case NVPTX::BI__nvvm_fma_mixed_rz_f16_f32:
1296-
case NVPTX::BI__nvvm_fma_mixed_rz_bf16_f32:
1297-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rz_f32, E,
1298-
*this);
1299-
case NVPTX::BI__nvvm_fma_mixed_rm_f16_f32:
1300-
case NVPTX::BI__nvvm_fma_mixed_rm_bf16_f32:
1301-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rm_f32, E,
1302-
*this);
1303-
case NVPTX::BI__nvvm_fma_mixed_rp_f16_f32:
1304-
case NVPTX::BI__nvvm_fma_mixed_rp_bf16_f32:
1305-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rp_f32, E,
1306-
*this);
1307-
case NVPTX::BI__nvvm_fma_mixed_rn_sat_f16_f32:
1308-
case NVPTX::BI__nvvm_fma_mixed_rn_sat_bf16_f32:
1309-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rn_sat_f32,
1310-
E, *this);
1311-
case NVPTX::BI__nvvm_fma_mixed_rz_sat_f16_f32:
1312-
case NVPTX::BI__nvvm_fma_mixed_rz_sat_bf16_f32:
1313-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rz_sat_f32,
1314-
E, *this);
1315-
case NVPTX::BI__nvvm_fma_mixed_rm_sat_f16_f32:
1316-
case NVPTX::BI__nvvm_fma_mixed_rm_sat_bf16_f32:
1317-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rm_sat_f32,
1318-
E, *this);
1319-
case NVPTX::BI__nvvm_fma_mixed_rp_sat_f16_f32:
1320-
case NVPTX::BI__nvvm_fma_mixed_rp_sat_bf16_f32:
1321-
return MakeMixedPrecisionFPArithmetic(Intrinsic::nvvm_fma_mixed_rp_sat_f32,
1322-
E, *this);
13231200
default:
13241201
return nullptr;
13251202
}

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