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[DAGCombiner] Handle type-promoted constants in SDIV exact lowering (#169950)
Builds up on the solution proposed for #169491 and #169924 and applies it for SDIV exact as well. Almost a carbon copy of UDIV exact solution from #169949.
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2 files changed

+26
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llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6345,7 +6345,6 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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EVT VT = N->getValueType(0);
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EVT SVT = VT.getScalarType();
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EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
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EVT ShSVT = ShVT.getScalarType();
63516350

@@ -6355,6 +6354,8 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
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auto BuildSDIVPattern = [&](ConstantSDNode *C) {
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if (C->isZero())
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return false;
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EVT CT = C->getValueType(0);
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APInt Divisor = C->getAPIntValue();
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unsigned Shift = Divisor.countr_zero();
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if (Shift) {
@@ -6363,12 +6364,13 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
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}
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APInt Factor = Divisor.multiplicativeInverse();
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Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT));
6366-
Factors.push_back(DAG.getConstant(Factor, dl, SVT));
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Factors.push_back(DAG.getConstant(Factor, dl, CT));
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return true;
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};
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// Collect all magic values from the build vector.
6371-
if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern))
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if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern, /*AllowUndefs=*/false,
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/*AllowTruncation=*/true))
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return SDValue();
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SDValue Shift, Factor;

llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,3 +75,24 @@ define <16 x i16> @srem_v16i16_by_7(<16 x i16> %x) {
7575
%rem = srem <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %rem
7777
}
78+
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define <8 x i16> @sdiv_exact_v8i16_by_255(<8 x i16> %x) {
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; CHECK-LABEL: sdiv_exact_v8i16_by_255:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvni v1.8h, #1, lsl #8
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; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%div = sdiv exact <8 x i16> %x, splat (i16 255)
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ret <8 x i16> %div
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}
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define <16 x i16> @sdiv_exact_v16i16_by_255(<16 x i16> %x) {
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; CHECK-LABEL: sdiv_exact_v16i16_by_255:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvni v2.8h, #1, lsl #8
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; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: mul v1.8h, v1.8h, v2.8h
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; CHECK-NEXT: ret
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%div = sdiv exact <16 x i16> %x, splat (i16 255)
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ret <16 x i16> %div
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}

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