[AArch64][DebugInfo]Add Target hooks for InstrRef on AArch64 #165953
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@llvm/pr-subscribers-debuginfo @llvm/pr-subscribers-llvm-globalisel Author: Shubham Sandeep Rastogi (rastogishubham) ChangesThis patch adds the target hooks required by Instruction Referencing for the AArch64 target, as mentioned in https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks Which allows the Instruction Referenced LiveDebugValues Pass to track spills and restore instructions. With this patch we can use the coverage with dbg_value: coverage with InstrRef without target hooks fix: coverage with InstrRef with target hooks fix: I believe this should be a good indication that Instruction Referencing should be turned on for AArch64? Patch is 2.76 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/165953.diff 181 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index ccc8eb8a9706d..17c2f8d07ea1c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2392,11 +2392,10 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
return false;
}
-Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameLoadOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRBui:
@@ -2405,22 +2404,26 @@ Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case AArch64::LDRDui:
case AArch64::LDRQui:
case AArch64::LDR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
-
return 0;
}
-Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameStoreOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::STRWui:
case AArch64::STRXui:
case AArch64::STRBui:
@@ -2429,16 +2432,55 @@ Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case AArch64::STRDui:
case AArch64::STRQui:
case AArch64::STR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
return 0;
}
+Register AArch64InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
+ return Reg;
+
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ }
+ return Register();
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
+ if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
+ return Reg;
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ }
+ return Register();
+}
+
/// Check all MachineMemOperands for a hint to suppress pairing.
bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) {
return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 179574a73aa01..44863eb2f6d95 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -205,6 +205,15 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
+ /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
+ /// stack locations as well. This uses a heuristic so it isn't
+ /// reliable for correctness.
+ Register isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
+ Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
/// Does this instruction set its full destination register to zero?
static bool isGPRZero(const MachineInstr &MI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
index 1fe63c9be8c62..be51210882eaa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -89,23 +89,23 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -113,9 +113,9 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -216,23 +216,23 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -240,9 +240,9 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -343,23 +343,23 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_release_acquire:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -367,9 +367,9 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -470,23 +470,23 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -494,9 +494,9 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -580,22 +580,22 @@ define void @atomic_load_relaxed(i64, i64, ptr %p, ptr %p2) {
; CHECK-OUTLINE-LLSC-O0-LABEL: atomic_load_relaxed:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x4, x2
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, xzr
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_relax
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x3]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -690,17 +690,17 @@ define i128 @val_compare_and_swap_return(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_return:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index e6bf3ab674717..3f51ec747182a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -56,10 +56,10 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -133,10 +133,10 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov x8, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w1, [x8]
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
@@ -211,10 +211,10 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -285,10 +285,10 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov x0, x1
; CHECK-OUTLINE-O0-NEXT: mov x1, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_relax
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-aarch64 Author: Shubham Sandeep Rastogi (rastogishubham) ChangesThis patch adds the target hooks required by Instruction Referencing for the AArch64 target, as mentioned in https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks Which allows the Instruction Referenced LiveDebugValues Pass to track spills and restore instructions. With this patch we can use the coverage with dbg_value: coverage with InstrRef without target hooks fix: coverage with InstrRef with target hooks fix: I believe this should be a good indication that Instruction Referencing should be turned on for AArch64? Patch is 2.76 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/165953.diff 181 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index ccc8eb8a9706d..17c2f8d07ea1c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2392,11 +2392,10 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
return false;
}
-Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameLoadOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRBui:
@@ -2405,22 +2404,26 @@ Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case AArch64::LDRDui:
case AArch64::LDRQui:
case AArch64::LDR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
-
return 0;
}
-Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameStoreOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::STRWui:
case AArch64::STRXui:
case AArch64::STRBui:
@@ -2429,16 +2432,55 @@ Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case AArch64::STRDui:
case AArch64::STRQui:
case AArch64::STR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
return 0;
}
+Register AArch64InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
+ return Reg;
+
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ }
+ return Register();
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
+ if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
+ return Reg;
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ }
+ return Register();
+}
+
/// Check all MachineMemOperands for a hint to suppress pairing.
bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) {
return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 179574a73aa01..44863eb2f6d95 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -205,6 +205,15 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
+ /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
+ /// stack locations as well. This uses a heuristic so it isn't
+ /// reliable for correctness.
+ Register isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
+ Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
/// Does this instruction set its full destination register to zero?
static bool isGPRZero(const MachineInstr &MI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
index 1fe63c9be8c62..be51210882eaa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -89,23 +89,23 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -113,9 +113,9 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -216,23 +216,23 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -240,9 +240,9 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -343,23 +343,23 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_release_acquire:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -367,9 +367,9 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -470,23 +470,23 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -494,9 +494,9 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -580,22 +580,22 @@ define void @atomic_load_relaxed(i64, i64, ptr %p, ptr %p2) {
; CHECK-OUTLINE-LLSC-O0-LABEL: atomic_load_relaxed:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x4, x2
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, xzr
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_relax
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x3]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -690,17 +690,17 @@ define i128 @val_compare_and_swap_return(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_return:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index e6bf3ab674717..3f51ec747182a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -56,10 +56,10 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -133,10 +133,10 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov x8, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w1, [x8]
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
@@ -211,10 +211,10 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -285,10 +285,10 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov x0, x1
; CHECK-OUTLINE-O0-NEXT: mov x1, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_relax
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-...
[truncated]
|
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| ; CHECK-OUTLINE-LLSC-O0: // %bb.0: | ||
| ; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32 | ||
| ; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill | ||
| ; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill |
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It might be easier to land an NFC PR that just regenerates all the comments ahead of time, then the follow-up patch becomes much smaller.
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Thanks for the review! I am confused about this comment however, how do I land a patch with all the comments changed without landing the code changes first? The code changes are the reasons the comments are needed right? I can put up a separate PR for the comments, but I still need the code changes to land first, otherwise the tests will fail till the code changes are landed.
This is why I split the PR into 2 commits, to make reviewing easier
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As far as I understand it, the massive comment updates are just a result of adding these functions, such that the assembly printing passes have more information available to them? In which case there's no way to split out the test changes from the implementation; it would be possible to add the hooks in separate commits so that the size of the individual commits are minimized, but I think that landing it all as one commit is better in this case: the main threat of changing so many files is if this commit has to be reverted after changes are placed on top of it, or if it similarly interferes with another revert; if that does happen though, splitting this into multiple commits would make the problem worse. Better to get it all done in one push imo, ymmv etc.
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Yes, the comment updates are because some "Folded Spills" have become "Spills" and "Folded Reloads" have become "Reloads"
We would not be able to land the test changes unless we upstream the code changes first, but I think I want to keep it as one commit, so everything goes together in the case of a revert. I will squash the patch before I submit the PR. Does everything look good to you otherwise @SLTozer ?
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Looks fine to me, ideally I'd want to be sure that @adrian-prantl is happy with the above explanation as to why this should all land in one patch - though since it was just a suggestion, maybe a final confirmation isn't necessary.
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Yep, I would also want another final comment from @adrian-prantl
Thanks!
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Works for me, the end result is desirable and if the updates come from adding the function it makes sense to land it all in one!
| if (Register Reg = isLoadFromStackSlot(MI, FrameIndex)) | ||
| return Reg; | ||
| SmallVector<const MachineMemOperand *, 1> Accesses; | ||
| if (hasLoadFromStackSlot(MI, Accesses)) { |
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Is hasLoadFromStackSlot guaranteed to place an element in Accesses when it returns true?
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Yes, hasLoadFromStackSlot only returns true if Accesses.size() changes, and Accesses is only being push_back()ed to, therefore, if hasLoadFromStackSlot returns true, it definitely placed an element in Accesses
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Conceptually this LGTM. I would recommend landing the NFC test update that regenerates the comments first though.
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| @@ -792,316 +792,5 @@ define void @zpr_and_ppr_local_stack_probing(<vscale x 16 x i1> %pred, <vscale x | |||
| store volatile i64 %gpr, ptr %gpr_local | |||
| ret void | |||
| } | |||
|
|
|||
| ; Only PPR callee-saves + a VLA | |||
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Is this removed accidentally?
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Yes, thank you very much for looking over all the tests, it was removed accidentally, I have fixed that, I also looked over all the tests again just to make sure they were okay.
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Thanks for checking. LGTM.
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LGTM, with some nits, of which I think firming up the location of the DBG_VALUE_LIST in the check lines is the only critical part.
llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir
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According to llvm/docs/InstrRefDebugInfo.md, to support proper instruction referecing on any platform, the target specific `TargetInstrInfo::isLoadFromStackSlotPostFE` and `TargetInstrInfo::isStoreToStackSlotPostFE` functions are needed to be implemented for the Instruction Reference-based LiveDebugValues pass to identify spill and restore instructions. It also fixes up all tests that were broken with adding target hooks. The target hooks cause a lot of the spill and reload comments to go from "X-byte Folded spill" to "X-byte spill", and "Y-byte Folded reload" to "Y-byte reload". Most tests were updated by using llvm/utils/update_llc_test_checks.py, some had to be manually changed. This is a separate commit for reviewability sake, and will be squashed. I have also added 2 tests 1. llvm/test/DebugInfo/AArch64/instr-ref-target-hooks.ll 2. llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.ll This patch is attempting to reland llvm#162327
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This patch adds the target hooks required by Instruction Referencing for the AArch64 target, as mentioned in https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks
Which allows the Instruction Referenced LiveDebugValues Pass to track spills and restore instructions.
With this patch we can use the
llvm/utils/llvm-locstats/llvm-locstats.pyto see the coverage statistics on a clang.dSYM built with in RelWithDebInfo we can see:coverage with dbg_value:
coverage with InstrRef without target hooks fix:
coverage with InstrRef with target hooks fix:
I believe this should be a good indication that Instruction Referencing should be turned on for AArch64?