[llvm-exegesis] Add AArch64 operand initializers, SetRegTo #169912
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Make llvm-exegesis more usable on AArch64 by doing the following: Add some missing exegesis handling of register classes Add some missing LLVM AArch64 OperandTypes Llvm-exegesis can now handle many more instructions. Load/store instructions not yet supported by llvm-exegesis, until llvm#144895 lands. Change-Id: I945079ae290395a207e4cc4619d177a67f0d5a47
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@llvm/pr-subscribers-tools-llvm-exegesis @llvm/pr-subscribers-backend-aarch64 Author: Simon Wallis (simonwallis2) ChangesMake llvm-exegesis more usable on AArch64 by doing the following: Add some missing exegesis handling of register classes; Llvm-exegesis can now handle many more AArch64 instructions. AArch64 load/store instructions are not yet supported by llvm-exegesis, until #144895 lands. Patch is 42.02 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/169912.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 58a53af76e1b5..7832f3ae35718 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -375,12 +375,14 @@ def simm10Scaled : Operand<i64> {
let ParserMatchClass = SImm10s8Operand;
let DecoderMethod = "DecodeSImm<10>";
let PrintMethod = "printImmScale<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm9s16 : Operand<i64> {
let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>;
let DecoderMethod = "DecodeSImm<9>";
let PrintMethod = "printImmScale<16>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
// uimm6 predicate - True if the immediate is in the range [0, 63].
@@ -391,18 +393,22 @@ def UImm6Operand : AsmOperandClass {
def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm16 : Operand<i16>, ImmLeaf<i16, [{return Imm >= 0 && Imm < 65536;}]>{
let ParserMatchClass = AsmImmRange<0, 65535>;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def CmpBranchUImm6Operand_32b
@@ -433,24 +439,29 @@ def UImm6Minus1Operand : AsmOperandClass {
def uimm6p1_32b : Operand<i32> {
let ParserMatchClass = UImm6Plus1Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6p1_64b : Operand<i64> {
let ParserMatchClass = UImm6Plus1Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6m1_32b : Operand<i32> {
let ParserMatchClass = UImm6Minus1Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6m1_64b : Operand<i64> {
let ParserMatchClass = UImm6Minus1Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def SImm9Operand : SImmOperand<9>;
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let ParserMatchClass = SImm9Operand;
let DecoderMethod = "DecodeSImm<9>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
// imm0_255 predicate - True if the immediate is in the range [0,255].
@@ -458,48 +469,57 @@ def Imm0_255Operand : AsmImmRange<0,255>;
def uimm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
let ParserMatchClass = Imm0_255Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 256; }]> {
let ParserMatchClass = Imm0_255Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def SImm8Operand : SImmOperand<8>;
def simm8_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
let ParserMatchClass = SImm8Operand;
let DecoderMethod = "DecodeSImm<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm8_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 128; }]> {
let ParserMatchClass = SImm8Operand;
let DecoderMethod = "DecodeSImm<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def SImm6Operand : SImmOperand<6>;
def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]> {
let ParserMatchClass = SImm6Operand;
let DecoderMethod = "DecodeSImm<6>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def SImm5Operand : SImmOperand<5>;
def simm5_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -16 && Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm5_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -16 && Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm5_8b : Operand<i32>, ImmLeaf<i32, [{ return (int8_t)Imm >= -16 && (int8_t)Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
let PrintMethod = "printSImm<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm5_16b : Operand<i32>, ImmLeaf<i32, [{ return (int16_t)Imm >= -16 && (int16_t)Imm < 16; }]> {
let ParserMatchClass = SImm5Operand;
let DecoderMethod = "DecodeSImm<5>";
let PrintMethod = "printSImm<16>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
// simm7sN predicate - True if the immediate is a multiple of N in the range
@@ -512,16 +532,19 @@ def SImm7s16Operand : SImmScaledMemoryIndexed<7, 16>;
def simm7s4 : Operand<i32> {
let ParserMatchClass = SImm7s4Operand;
let PrintMethod = "printImmScale<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm7s8 : Operand<i32> {
let ParserMatchClass = SImm7s8Operand;
let PrintMethod = "printImmScale<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm7s16 : Operand<i32> {
let ParserMatchClass = SImm7s16Operand;
let PrintMethod = "printImmScale<16>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def am_sve_fi : ComplexPattern<iPTR, 2, "SelectAddrModeFrameIndexSVE", []>;
@@ -571,18 +594,21 @@ def uimm5s2 : Operand<i64>, ImmLeaf<i64,
UImmS2XForm> {
let ParserMatchClass = UImm5s2Operand;
let PrintMethod = "printImmScale<2>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm5s4 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }],
UImmS4XForm> {
let ParserMatchClass = UImm5s4Operand;
let PrintMethod = "printImmScale<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm5s8 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }],
UImmS8XForm> {
let ParserMatchClass = UImm5s8Operand;
let PrintMethod = "printImmScale<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
// tuimm5sN predicate - similar to uimm5sN, but use TImmLeaf (TargetConstant)
@@ -592,18 +618,21 @@ def tuimm5s2 : Operand<i64>, TImmLeaf<i64,
UImmS2XForm> {
let ParserMatchClass = UImm5s2Operand;
let PrintMethod = "printImmScale<2>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def tuimm5s4 : Operand<i64>, TImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }],
UImmS4XForm> {
let ParserMatchClass = UImm5s4Operand;
let PrintMethod = "printImmScale<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def tuimm5s8 : Operand<i64>, TImmLeaf<i64,
[{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }],
UImmS8XForm> {
let ParserMatchClass = UImm5s8Operand;
let PrintMethod = "printImmScale<8>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
// uimm6sN predicate - True if the immediate is a multiple of N in the range
@@ -616,26 +645,31 @@ def UImm6s16Operand : UImmScaledMemoryIndexed<6, 16>;
def uimm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6s1Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s2 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); }]> {
let PrintMethod = "printImmScale<2>";
let ParserMatchClass = UImm6s2Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s4 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); }]> {
let PrintMethod = "printImmScale<4>";
let ParserMatchClass = UImm6s4Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s8 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); }]> {
let PrintMethod = "printImmScale<8>";
let ParserMatchClass = UImm6s8Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def uimm6s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); }]> {
let PrintMethod = "printImmScale<16>";
let ParserMatchClass = UImm6s16Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def SImmS2XForm : SDNodeXForm<imm, [{
@@ -660,6 +694,7 @@ def SImm6s1Operand : SImmScaledMemoryIndexed<6, 1>;
def simm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -32 && Imm < 32; }]> {
let ParserMatchClass = SImm6s1Operand;
let DecoderMethod = "DecodeSImm<6>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
// simm4sN predicate - True if the immediate is a multiple of N in the range
@@ -675,6 +710,7 @@ def simm4s1 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-8 && Imm <= 7; }]> {
let ParserMatchClass = SImm4s1Operand;
let DecoderMethod = "DecodeSImm<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s2 : Operand<i64>, ImmLeaf<i64,
@@ -682,6 +718,7 @@ def simm4s2 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<2>";
let ParserMatchClass = SImm4s2Operand;
let DecoderMethod = "DecodeSImm<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s3 : Operand<i64>, ImmLeaf<i64,
@@ -689,6 +726,7 @@ def simm4s3 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<3>";
let ParserMatchClass = SImm4s3Operand;
let DecoderMethod = "DecodeSImm<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s4 : Operand<i64>, ImmLeaf<i64,
@@ -696,18 +734,21 @@ def simm4s4 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<4>";
let ParserMatchClass = SImm4s4Operand;
let DecoderMethod = "DecodeSImm<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; }], SImmS16XForm> {
let PrintMethod = "printImmScale<16>";
let ParserMatchClass = SImm4s16Operand;
let DecoderMethod = "DecodeSImm<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def simm4s32 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-256 && Imm <= 224 && (Imm % 32) == 0x0; }], SImmS32XForm> {
let PrintMethod = "printImmScale<32>";
let ParserMatchClass = SImm4s32Operand;
let DecoderMethod = "DecodeSImm<4>";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def Imm1_8Operand : AsmImmRange<1, 8>;
@@ -737,6 +778,7 @@ def MovWSymbolG3AsmOperand : AsmOperandClass {
def movw_symbol_g3 : Operand<i32> {
let ParserMatchClass = MovWSymbolG3AsmOperand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def MovWSymbolG2AsmOperand : AsmOperandClass {
@@ -746,6 +788,7 @@ def MovWSymbolG2AsmOperand : AsmOperandClass {
def movw_symbol_g2 : Operand<i32> {
let ParserMatchClass = MovWSymbolG2AsmOperand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def MovWSymbolG1AsmOperand : AsmOperandClass {
@@ -755,6 +798,7 @@ def MovWSymbolG1AsmOperand : AsmOperandClass {
def movw_symbol_g1 : Operand<i32> {
let ParserMatchClass = MovWSymbolG1AsmOperand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def MovWSymbolG0AsmOperand : AsmOperandClass {
@@ -764,6 +808,7 @@ def MovWSymbolG0AsmOperand : AsmOperandClass {
def movw_symbol_g0 : Operand<i32> {
let ParserMatchClass = MovWSymbolG0AsmOperand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
class fixedpoint_i32<ValueType FloatVT>
@@ -772,6 +817,7 @@ class fixedpoint_i32<ValueType FloatVT>
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm32";
let ParserMatchClass = Imm1_32Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
class fixedpoint_i64<ValueType FloatVT>
@@ -780,6 +826,7 @@ class fixedpoint_i64<ValueType FloatVT>
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm64";
let ParserMatchClass = Imm1_64Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def fixedpoint_f16_i32 : fixedpoint_i32<f16>;
@@ -795,6 +842,7 @@ class fixedpoint_recip_i32<ValueType FloatVT>
ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<32>", [fpimm, ld]> {
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm32";
+ let OperandType = "OPERAND_IMMEDIATE";
}
class fixedpoint_recip_i64<ValueType FloatVT>
@@ -802,6 +850,7 @@ class fixedpoint_recip_i64<ValueType FloatVT>
ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<64>", [fpimm, ld]> {
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm64";
+ let OperandType = "OPERAND_IMMEDIATE";
}
def fixedpoint_recip_f16_i32 : fixedpoint_recip_i32<f16>;
@@ -818,6 +867,7 @@ def vecshiftR8 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR8OpValue";
let DecoderMethod = "DecodeVecShiftR8Imm";
let ParserMatchClass = Imm1_8Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR16 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
@@ -825,6 +875,7 @@ def vecshiftR16 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR16OpValue";
let DecoderMethod = "DecodeVecShiftR16Imm";
let ParserMatchClass = Imm1_16Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR16Narrow : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
@@ -832,6 +883,7 @@ def vecshiftR16Narrow : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR16OpValue";
let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
let ParserMatchClass = Imm1_8Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR32 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
@@ -839,6 +891,7 @@ def vecshiftR32 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR32OpValue";
let DecoderMethod = "DecodeVecShiftR32Imm";
let ParserMatchClass = Imm1_32Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR32Narrow : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
@@ -846,6 +899,7 @@ def vecshiftR32Narrow : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR32OpValue";
let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
let ParserMatchClass = Imm1_16Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
@@ -853,6 +907,7 @@ def vecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR64OpValue";
let DecoderMethod = "DecodeVecShiftR64Imm";
let ParserMatchClass = Imm1_64Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftR64Narrow : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
@@ -860,6 +915,7 @@ def vecshiftR64Narrow : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftR64OpValue";
let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
let ParserMatchClass = Imm1_32Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def Imm0_0Operand : AsmImmRange<0, 0>;
@@ -879,6 +935,7 @@ def vecshiftL8 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL8OpValue";
let DecoderMethod = "DecodeVecShiftL8Imm";
let ParserMatchClass = Imm0_7Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftL16 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 16);
@@ -886,6 +943,7 @@ def vecshiftL16 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL16OpValue";
let DecoderMethod = "DecodeVecShiftL16Imm";
let ParserMatchClass = Imm0_15Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftL32 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 32);
@@ -893,6 +951,7 @@ def vecshiftL32 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL32OpValue";
let DecoderMethod = "DecodeVecShiftL32Imm";
let ParserMatchClass = Imm0_31Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def vecshiftL64 : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 64);
@@ -900,6 +959,7 @@ def vecshiftL64 : Operand<i32>, TImmLeaf<i32, [{
let EncoderMethod = "getVecShiftL64OpValue";
let DecoderMethod = "DecodeVecShiftL64Imm";
let ParserMatchClass = Imm0_63Operand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
@@ -1199,6 +1259,8 @@ class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
let PrintMethod = "printShiftedRegister";
let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
+ let OperandType = "OPERAND_SHIFTED_REGISTER";
+ let OperandNamespace = "AArch64";
}
def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
@@ -1219,6 +1281,7 @@ class logical_shift<int width> : Operand<i32> {
let PrintMethod = "printShifter";
let ParserMatchClass = !cast<AsmOperandClass>(
"LogicalShifterOperand" # width);
+ let OperandType = "OPERAND_IMMEDIATE";
}
def logical_shift32 : logical_shift<32>;
@@ -1229,6 +1292,8 @@ class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
let PrintMethod = "printShiftedRegister";
let MIOperandInfo = (ops regclass, shiftop);
+ let OperandType = "OPERAND_SHIFTED_REGISTER";
+ let OperandNamespace = "AArch64";
}
def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
@@ -1249,6 +1314,8 @@ def logical_vec_shift : Operand<i32> {
let PrintMethod = "printShifter";
let EncoderMethod = "getVecShifterOpValue";
let ParserMatchClass = LogicalVecShifterOperand;
+ let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
+ let OperandNamespace = "AArch64";
}
// A logical vector half-word shifter operand:
@@ -1258,6 +1325,8 @@ def logical_vec_hw_shift : Operand<i32> {
let PrintMethod = "printShifter";
let EncoderMethod = "getVecShifterOpValue";
let ParserMatchClass = LogicalVecHalfWordShifterOperand;
+ let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
+ let OperandNamespace = "AArch64";
}
// A vector move shifter operand:
@@ -1292,6 +1361,8 @@ class addsub_shifted_imm<ValueType Ty>
let EncoderMethod = "getAddSubImmOpValue";
let ParserMatchClass = AddSubImmOperand;
let MIOperandInfo = (ops i32imm, i32imm);
+ let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
+ let OperandNamespace = "AArch64";
}
class addsub_shifted_imm_neg<ValueType Ty>
@@ -1299,6 +1370,8 @@ class addsub_shifted_imm_neg<ValueType Ty>
let EncoderMethod = "getAddSubImmOpValue";
let ParserMatchClass = AddSubImmNegOperand;
let MIOperandInfo = (ops i32imm, i32imm);
+ let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
+ let OperandNamespace = "AArch64";
}
def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
@@ -1320,6 +1393,8 @@ class neg_addsub_shifted_imm<ValueType Ty>
let EncoderMethod = "getAddSubImmOpValue";
let ParserMatchClass = AddSubImmOperand;
let MIOperandInfo = (ops i32imm, i32imm);
+ let OperandType = "OPERAND_SHIFTED_IMMEDIATE";
+ let OperandNamespace = "AArch64";
}
def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
@@ -1339,28 +1414,35 @@ def gi_neg_addsub_shifted_imm64 :
def arith_extend : Operand<i32> {
let PrintMethod = "printArithExtend";
let ParserMatchClass = ExtendOperand;
+ let OperandType = "OPERAND_IMMEDIATE";
}
def arith_extend64 : Operand<i32> {
let PrintMethod = "printArithExtend";
let ParserMatchClass = ExtendOperand64;
+ let OperandType = "OPERAND_IMMEDIATE";
}
// 'extend' that's a lsl of a 64-bit register.
def arith_extendlsl64 : Operand<i32> {
let PrintMethod = "printArithExtend";
let ParserMatchClass = ExtendOperandLSL64;
+ let OperandType = "OPERAND_IMMEDIATE";
}
class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
let PrintMethod = "printExtendedRegister";
let MIOperandInfo = (ops GPR32, arith_extend);
+ let OperandType = "OPERAND_SHIFTED_REGISTER";
+ let OperandNamespace = "AArch64";
}
class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
let PrintMethod = "printExtendedRegister";
let MIOperandInfo = (ops GPR32, arith_extend64);
+ let OperandType = "OPERAND_SHIFTED_REGISTER";
+ let OperandNamespace = "AArch64";
}
def arith_extended_reg32_i32 : ar...
[truncated]
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✅ With the latest revision this PR passed the C/C++ code formatter. |
Make llvm-exegesis more usable on AArch64 by doing the following: Add some missing exegesis handling of register classes Add some missing LLVM AArch64 OperandTypes Llvm-exegesis can now handle many more instructions. Load/store instructions not yet supported by llvm-exegesis, until llvm#144895 lands. Change-Id: I73d22942943ee5882e89852f538cf1805645def5
Make llvm-exegesis more usable on AArch64 by doing the following: Add some missing exegesis handling of register classes Add some missing LLVM AArch64 OperandTypes Llvm-exegesis can now handle many more instructions. Load/store instructions not yet supported by llvm-exegesis, until llvm#144895 lands. Change-Id: I344efdcfa66b05321125f21c20f7556da583e7ee
simonwallis2
commented
Nov 28, 2025
| defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand, | ||
| [{ return ((uint32_t)Imm) == 0; }]>; | ||
| } | ||
| let OperandType = "OPERAND_IMMEDIATE" in { |
Contributor
Author
There was a problem hiding this comment.
I considered indenting the clauses inside the let.
An arguments against is that this change is clearer without it.
simonwallis2
commented
Nov 28, 2025
| def SVEVectorIndexExtDupDOperand : AsmVectorIndex<0, 7, "SVE">; | ||
| def SVEVectorIndexExtDupQOperand : AsmVectorIndex<0, 3, "SVE">; | ||
|
|
||
| let OperandType = "OPERAND_IMMEDIATE" in { |
Contributor
Author
There was a problem hiding this comment.
I considered indenting the clauses inside the let.
This file already has inconsistent formatting.
Contributor
Author
|
I see little benefit in adding new tests for this commit. |
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Make llvm-exegesis more usable on AArch64 by doing the following:
Add some missing exegesis handling of register classes;
Add some missing LLVM AArch64 OperandTypes.
Llvm-exegesis can now handle many more AArch64 instructions.
AArch64 load/store instructions are not yet supported by llvm-exegesis, until #144895 lands.