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[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) #170076

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[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) #170076

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701bcdf
[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0)
Dec 1, 2025
2cc21b2
Update llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
rez5427 Dec 3, 2025
87c6428
Use getZExtOrTrunc
rez5427 Dec 4, 2025
0c20d33
Add getBoolExtOrTrunc and and
rez5427 Dec 4, 2025
ae1bccf
Add freeze, ban vector
rez5427 Dec 6, 2025
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12 changes: 12 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10877,6 +10877,18 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
assert(VT == RHS.getValueType() && "Expected operands to be the same type");
assert(VT.isInteger() && "Expected operands to be integers");

// usub.sat(a, 1) -> sub(a, zext(a != 0))
if (Opcode == ISD::USUBSAT && !VT.isVector() && isOneConstant(RHS)) {
LHS = DAG.getFreeze(LHS);
SDValue Zero = DAG.getConstant(0, dl, VT);
EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
SDValue IsNonZero = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETNE);
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@topperc topperc Dec 3, 2025

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Do we need to freeze LHS?

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@RKSimon RKSimon Dec 4, 2025

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https://alive2.llvm.org/ce/z/XSP_Sj

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@topperc topperc Dec 5, 2025

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That shows that it works with freeze. Looks like it fails if the freeze is removed?

SDValue Subtrahend = DAG.getBoolExtOrTrunc(IsNonZero, dl, VT, BoolVT);
Subtrahend =
DAG.getNode(ISD::AND, dl, VT, Subtrahend, DAG.getConstant(1, dl, VT));
return DAG.getNode(ISD::SUB, dl, VT, LHS, Subtrahend);
}

// usub.sat(a, b) -> umax(a, b) - b
if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) {
SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/and-mask-removal.ll
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Expand Up @@ -483,9 +483,9 @@ define i64 @pr58109(i8 signext %0) {
; CHECK-SD-LABEL: pr58109:
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: add w8, w0, #1
; CHECK-SD-NEXT: and w8, w8, #0xff
; CHECK-SD-NEXT: subs w8, w8, #1
; CHECK-SD-NEXT: csel w0, wzr, w8, lo
; CHECK-SD-NEXT: ands w8, w8, #0xff
; CHECK-SD-NEXT: cset w9, ne
; CHECK-SD-NEXT: sub w0, w8, w9
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: pr58109:
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28 changes: 28 additions & 0 deletions llvm/test/CodeGen/RISCV/usub_sat.ll
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Expand Up @@ -185,3 +185,31 @@ define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
}

define signext i32 @sat_dec_i32(i32 signext %x) nounwind {
; RV32I-LABEL: sat_dec_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: snez a1, a0
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sat_dec_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: snez a1, a0
; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: ret
;
; RV32IZbb-LABEL: sat_dec_i32:
; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: snez a1, a0
; RV32IZbb-NEXT: sub a0, a0, a1
; RV32IZbb-NEXT: ret
;
; RV64IZbb-LABEL: sat_dec_i32:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: snez a1, a0
; RV64IZbb-NEXT: subw a0, a0, a1
; RV64IZbb-NEXT: ret
%tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 1)
ret i32 %tmp
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/combine-sub-usat.ll
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Expand Up @@ -116,9 +116,9 @@ define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) {
define i32 @combine_dec_i32(i32 %a0) {
; CHECK-LABEL: combine_dec_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: subl $1, %edi
; CHECK-NEXT: cmovael %edi, %eax
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl $1, %edi
; CHECK-NEXT: adcl $-1, %eax
; CHECK-NEXT: retq
%1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 1)
ret i32 %1
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