Add tohost capabilities to the UVM env

* cv32e20/bsp/crt0.s: add tohost symbol declaration
* cv32e20/bsp/link.ld: add tohost symbol linking address
* cv32e20/bsp/syscalls.c: add tohost store in the exit function
* cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv: add rule to enforce
not ZERO reg used in the scratch reg. This constraint was already
implemented but not working with vsim
* cv32e20/env/uvme/uvme_cv32e20_env.sv: add mechanism to load symbols
from the binary for the execution exit.
* cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv: Adapt code
to host format ( {exit_value, 1} )
* cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv: substitute
uvm_objects_utils(begin/end) for a simple uvm_object_utils
* lib/corev-dv/corev_asm_program_gen.sv: delete wfi for locking the core
and add tohost mechanism
* lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_mon.sv: vsim
complaining for using passive_mp
* lib/uvm_libs/uvml_sb/uvml_sb_cntxt.sv: delete T_TRN type for event as
it causes vsim to fail simulation
* mk/Common.mk: add compilation for elfloader vendor
* mk/uvmt/vsim.mk: add comilation for elfloader vendor and delete
clean_riscv-dv on each corev-dv generation
* vendor/elfloader/Makefile: add elfloader vendor
* vendor/elfloader/elfloader.cc: add elfloader vendor

Author: Mario

cv32e20/bsp/Makefile

@@ -12,17 +12,17 @@ RISCV_GCC = $(RISCV_EXE_PREFIX)gcc
 RISCV_AR = $(RISCV_EXE_PREFIX)ar
 SRC = crt0.S handlers.S syscalls.c vectors.S
 OBJ = crt0.o handlers.o syscalls.o vectors.o
-LIBCV-VERIF = libcv-verif.a 
-CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(CV_SW_MARCH) -Wall -pedantic
+LIBCV-VERIF = libcv-verif.a
+CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic
 
 all: $(LIBCV-VERIF)
 
-$(LIBCV-VERIF): $(OBJ) 
+$(LIBCV-VERIF): $(OBJ)
 	$(RISCV_AR) rcs $@ $(OBJ)
 
 %.o : %.c
 	$(RISCV_GCC) $(CFLAGS) -c $< -o $@
-	
+
 %.o : %.S
 	$(RISCV_GCC) $(CFLAGS) -c $< -o $@
 

cv32e20/bsp/crt0.S

@@ -70,3 +70,11 @@ _fini:
 	ret
 .size  _init, .-_init
 .size _fini, .-_fini
+
+.section ".tohost","aw",@progbits
+.align 6
+.globl tohost
+tohost: .dword 0
+.align 6
+.globl fromhost
+fromhost: .dword 0

cv32e20/bsp/link.ld

@@ -65,6 +65,8 @@ SECTIONS
     KEEP(*(.vectors));
   } >ram
 
+  .tohost : { *(.tohost) } >ram
+
   /* Read-only sections, merged into text segment: */
   PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS;
   .interp         : { *(.interp) } >ram

cv32e20/bsp/syscalls.c

@@ -31,6 +31,8 @@
 #include <assert.h>
 #undef errno
 extern int errno;
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
 
 /* write to this reg for outputting strings */
 #define STDOUT_REG 0x10000000
@@ -111,6 +113,7 @@ int _execve(const char *name, char *const argv[], char *const env[])
 
 void _exit(int exit_status)
 {
+  tohost = (exit_status << 1) | 1;
   *(volatile int *)EXIT_REG = exit_status;
   asm volatile("wfi");
   /* _exit should not return */

cv32e20/env/corev-dv/cv32e20_instr_gen_config.sv

@@ -42,7 +42,7 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config;
     // Debug pointer may not be the return address, stack pointer, nor thread pointer
     if (!gen_debug_section) {
       dp == ZERO;
-    } else {      
+    } else {
       !(dp inside {sp, tp, ra, scratch_reg, GP, RA, ZERO});
       foreach (gpr[i]) {
         !(gpr[i] inside {dp});
@@ -64,15 +64,19 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config;
                                       };
   }
 
+  constraint scratch_reg_c_not_zero {
+      scratch_reg != ZERO;
+  }
+
   constraint fast_intr_handler_c {
     if (!enable_fast_interrupt_handler) {
       knob_zero_fast_intr_handlers == 1;
     }
-    
+
     // Nver use fast handler for exceptions (interrupt 0)
     use_fast_intr_handler[0] == 0;
 
-    knob_zero_fast_intr_handlers -> !use_fast_intr_handler;    
+    knob_zero_fast_intr_handlers -> !use_fast_intr_handler;
 
     // VECTORED mode required for any fast interrupts
     if (use_fast_intr_handler) {
@@ -86,7 +90,7 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config;
     `uvm_field_enum(riscv_reg_t, dp, UVM_DEFAULT)
     `uvm_field_enum(riscv_reg_t, scratch_reg, UVM_DEFAULT)
     `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT)
-    `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT)    
+    `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT)
   `uvm_object_utils_end
 
   function new(string name="");
@@ -105,13 +109,13 @@ class cv32e20_instr_gen_config extends riscv_instr_gen_config;
 
     // In the debug ROM some combinations are not valid because they use the same register (dscratch0)
     if (gen_debug_section) begin
-      if ((enable_ebreak_in_debug_rom || set_dcsr_ebreak) && 
+      if ((enable_ebreak_in_debug_rom || set_dcsr_ebreak) &&
            enable_debug_single_step) begin
-        `uvm_fatal("CVINSTGENCFG", 
+        `uvm_fatal("CVINSTGENCFG",
                    $sformatf("Illegal combination of debug plusargs: enable_ebreak_in_debug_rom = %0d, set_dcsr_ebreakl = %0d, enable_debug_single_step = %0d",
                              enable_ebreak_in_debug_rom, set_dcsr_ebreak, enable_debug_single_step))
       end
-    end    
+    end
   endfunction : post_randomize
 
 endclass : cv32e20_instr_gen_config

cv32e20/env/uvme/uvme_cv32e20_env.sv

@@ -26,6 +26,8 @@ typedef class uvme_cv32e20_vp_sig_writer_seq_c;
 typedef class uvme_cv32e20_vp_status_flags_seq_c;
 typedef class uvme_cv32e20_vp_rand_num_seq_c;
 
+import "DPI-C" function longint read_symbol(input string symbol, output longint unsigned address);
+import "DPI-C" function read_elf(input string filename);
 /**
  * Top-level component that encapsulates, builds and connects all other
  * CV32E20 environment components.
@@ -50,6 +52,7 @@ class uvme_cv32e20_env_c extends uvm_env;
    uvma_obi_memory_agent_c  obi_memory_data_agent ;
 
 
+   longint unsigned vp_rand_num, vp_sig_writer, vp_status_flags, vp_interrupt_timer, vp_debug_control;
 
    `uvm_component_utils_begin(uvme_cv32e20_env_c)
       `uvm_field_object(cfg  , UVM_DEFAULT)
@@ -142,6 +145,11 @@ class uvme_cv32e20_env_c extends uvm_env;
     */
    extern virtual function void assemble_vsequencer();
 
+   /**
+    * Load binary into elfloader to enable aux functions
+    */
+   extern virtual function void load_binary();
+
 endclass : uvme_cv32e20_env_c
 
 
@@ -181,6 +189,7 @@ function void uvme_cv32e20_env_c::build_phase(uvm_phase phase);
       create_env_components();
 
       if (cfg.is_active) begin
+         load_binary();
          create_vsequencer();
       end
 
@@ -250,39 +259,39 @@ task uvme_cv32e20_env_c::run_phase(uvm_phase phase);
             //void'(data_slv_seq.register_vp_vseq("vp_rand_num", 32'h1500_1000, 1, uvma_obi_memory_vp_rand_num_seq_c::get_type()));
             begin
                uvme_cv32e20_vp_rand_num_seq_c vp_seq;
-               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_rand_num", 32'h1500_1000, uvme_cv32e20_vp_rand_num_seq_c::get_type()))) begin
+               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_rand_num", vp_rand_num, uvme_cv32e20_vp_rand_num_seq_c::get_type()))) begin
                   `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_rand_num correctly"));
                end
                vp_seq.cv32e20_cntxt = cntxt;
             end
 
             begin
                uvme_cv32e20_vp_sig_writer_seq_c vp_seq;
-               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", 32'h2000_0008, uvme_cv32e20_vp_sig_writer_seq_c::get_type()))) begin
+               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", vp_sig_writer, uvme_cv32e20_vp_sig_writer_seq_c::get_type()))) begin
                   `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_sig_writes correctly"));
                end
                vp_seq.cv32e20_cntxt = cntxt;
             end
 
             begin
                uvme_cv32e20_vp_status_flags_seq_c vp_seq;
-               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", 32'h2000_0000, uvme_cv32e20_vp_status_flags_seq_c::get_type()))) begin
+               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", vp_status_flags, uvme_cv32e20_vp_status_flags_seq_c::get_type()))) begin
                   `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_status_flags correctly"));
                end
                vp_seq.cv32e20_cntxt = cntxt;
             end
 
             begin
                uvme_cv32e20_vp_interrupt_timer_seq_c vp_seq;
-               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", 32'h1500_0000, uvme_cv32e20_vp_interrupt_timer_seq_c::get_type()))) begin
+               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", vp_interrupt_timer, uvme_cv32e20_vp_interrupt_timer_seq_c::get_type()))) begin
                   `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_interrupt_timer correctly"));
                end
                vp_seq.cv32e20_cntxt = cntxt;
             end
 
             begin
                uvme_cv32e20_vp_debug_control_seq_c vp_seq;
-               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", 32'h1500_0008, uvme_cv32e20_vp_debug_control_seq_c::get_type()))) begin
+               if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", vp_debug_control, uvme_cv32e20_vp_debug_control_seq_c::get_type()))) begin
                   `uvm_fatal("CV32E20VPSEQ", $sformatf("Could not cast vp_debug_control correctly"));
                end
                vp_seq.cv32e20_cntxt = cntxt;
@@ -449,5 +458,24 @@ function void uvme_cv32e20_env_c::assemble_vsequencer();
 endfunction: assemble_vsequencer
 
 
+function void uvme_cv32e20_env_c::load_binary();
+    string binary;
+
+    vp_rand_num = 32'h1500_1000;
+    vp_sig_writer = 32'h2000_0008;
+    vp_status_flags = 32'h2000_0000;
+    vp_interrupt_timer = 32'h1500_0000;
+    vp_debug_control = 32'h1500_0008;
+
+    if ($value$plusargs("elf_file=%s", binary))
+    begin
+        read_elf(binary);
+        read_symbol("tohost", vp_status_flags);
+        `uvm_info("cv32e20_env", $sformatf("Loading TOHOST symbol: %h", vp_status_flags), UVM_LOW)
+    end
+
+
+endfunction: load_binary
+
 `endif // __UVME_CV32E20_ENV_SV__
 

cv32e20/env/uvme/vseq/uvme_cv32e20_vp_status_flags_seq.sv

@@ -1,27 +1,27 @@
-// 
+//
 // Copyright 2021 OpenHW Group
 // Copyright 2021 Silicon Labs
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// 
+//
 // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
 // not use this file except in compliance with the License, or, at your option,
 // the Apache License version 2.0. You may obtain a copy of the License at
-// 
+//
 //     https://solderpad.org/licenses/SHL-2.1/
-// 
+//
 // Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
 // License for the specific language governing permissions and limitations
 // under the License.
-// 
+//
 
 `ifndef __UVME_CV32E20_VP_STATUS_FLAGS_SEQ_SV__
 `define __UVME_CV32E20_VP_STATUS_FLAGS_SEQ_SV__
 
 
 /**
- * Sequence implementing the virtual status flags decoding 
+ * Sequence implementing the virtual status flags decoding
  */
 class uvme_cv32e20_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c;
 
@@ -31,7 +31,7 @@ class uvme_cv32e20_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c;
 
    `uvm_object_utils_begin(uvme_cv32e20_vp_status_flags_seq_c)
    `uvm_object_utils_end
-      
+
    /**
     * Default constructor.
     */
@@ -55,9 +55,9 @@ class uvme_cv32e20_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c;
 endclass : uvme_cv32e20_vp_status_flags_seq_c
 
 function uvme_cv32e20_vp_status_flags_seq_c::new(string name="uvme_cv32e20_vp_status_flags_seq_c");
-   
+
    super.new(name);
-   
+
 endfunction : new
 
 function int unsigned uvme_cv32e20_vp_status_flags_seq_c::get_num_words();
@@ -81,31 +81,26 @@ task uvme_cv32e20_vp_status_flags_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_t
    uvma_obi_memory_slv_seq_item_c  slv_rsp;
 
    `uvm_create(slv_rsp)
-   
-   slv_rsp.orig_trn = mon_trn;   
+
+   slv_rsp.orig_trn = mon_trn;
    slv_rsp.err = 1'b0;
 
    if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin
       `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'vp_status_flags':\n%s", mon_trn.sprint()), UVM_DEBUG)
       case (get_vp_index(mon_trn))
          0: begin
-            if (mon_trn.data == 'd123456789) begin
-               `uvm_info("VP_VSEQ", "virtual peripheral: TEST PASSED", UVM_DEBUG)
+            if (mon_trn.data[0] == 1) begin
                cv32e20_cntxt.vp_status_vif.tests_passed = 1;
                cv32e20_cntxt.vp_status_vif.exit_valid   = 1;
-               cv32e20_cntxt.vp_status_vif.exit_value   = 0;
-            end
-            else if (mon_trn.data == 'd1) begin
-               cv32e20_cntxt.vp_status_vif.tests_failed = 1;
-               cv32e20_cntxt.vp_status_vif.exit_valid   = 1;
-               cv32e20_cntxt.vp_status_vif.exit_value   = 1;
+               cv32e20_cntxt.vp_status_vif.exit_value   = mon_trn.data >> 1;
+               `uvm_info("VP_VSEQ", $sformatf("virtual peripheral: TEST PASSED WITH CODE %h", cv32e20_cntxt.vp_status_vif.exit_value), UVM_DEBUG)
             end
          end
          1: begin
             `uvm_info("VP_VSEQ", "virtual peripheral: END OF SIM", UVM_DEBUG)
             cv32e20_cntxt.vp_status_vif.exit_valid = 1;
             cv32e20_cntxt.vp_status_vif.exit_value = mon_trn.data;
-         end      
+         end
       endcase
    end
    else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin

cv32e20/tb/uvmt/uvmt_cv32e20_dut_wrap.sv

@@ -117,8 +117,8 @@ module uvmt_cv32e20_dut_wrap #(
 
     // ------------------------------------------------------------------------
     // Instantiate the core
-//    cve2_top #( 
-    cve2_top_tracing #( 
+//    cve2_top #(
+    cve2_top_tracing #(
                .MHPMCounterNum   (MHPMCounterNum),
                .MHPMCounterWidth (MHPMCounterWidth),
                .RV32E            (RV32E),
@@ -136,7 +136,7 @@ module uvmt_cv32e20_dut_wrap #(
          .ram_cfg_i              ( prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT ),
 
          .hart_id_i              ( 32'h0000_0000                  ),
-         .boot_addr_i            ( 32'h0000_0000                  ), //<---MJS changing to 0 
+         .boot_addr_i            ( 32'h0000_0000                  ), //<---MJS changing to 0
 
   // Instruction memory interface
          .instr_req_o            ( obi_memory_instr_if.req        ), // core to agent

cv32e40p/env/uvme/uvme_rv32isa_covg_trn.sv

@@ -1,12 +1,12 @@
 // Copyright 2020 OpenHW Group
 // Copyright 2020 Silicon Labs, Inc.
-// 
+//
 // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-// 
+//
 //     https://solderpad.org/licenses/
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -25,18 +25,17 @@
    through UVM testbench
  */
 class uvme_rv32isa_covg_trn_c extends uvml_trn_mon_trn_c;
-   
+    // Note, structs are not supported in the uvm field macros
+    `uvm_object_utils(uvme_rv32isa_covg_trn_c)
+
     ins_t ins;
 
-    // Note, structs are not supported in the uvm field macros
-    `uvm_object_utils_begin(uvme_rv32isa_covg_trn_c)   
-    `uvm_object_utils_end
-    
+
     /**
     * Default constructor.
     */
     extern function new(string name="uvme_rv32isa_covg_trn");
-   
+
     extern function void do_copy(uvm_object rhs);
     extern function void do_print(uvm_printer printer);
 
@@ -46,9 +45,9 @@ endclass : uvme_rv32isa_covg_trn_c
 `pragma protect begin
 
 function uvme_rv32isa_covg_trn_c::new(string name="uvme_rv32isa_covg_trn");
-   
+
    super.new(name);
-   
+
 endfunction : new
 
 function void uvme_rv32isa_covg_trn_c::do_copy(uvm_object rhs);
@@ -57,7 +56,7 @@ function void uvme_rv32isa_covg_trn_c::do_copy(uvm_object rhs);
     super.do_copy(rhs);
     assert($cast(rhs_trn, rhs));
 
-    this.ins.ins_str = rhs_trn.ins.ins_str;    
+    this.ins.ins_str = rhs_trn.ins.ins_str;
     this.ins.asm     = rhs_trn.ins.asm;
     foreach (this.ins.ops[i]) begin
         this.ins.ops[i].key = rhs_trn.ins.ops[i].key;