|
3 | 3 | Exceptions and Interrupts |
4 | 4 | ========================= |
5 | 5 |
|
6 | | -Ibex implements trap handling for interrupts and exceptions according to the `RISC-V Privileged Specification, version 20211203 <https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view>`. |
| 6 | +Ibex implements trap handling for interrupts and exceptions according to the `RISC-V Privileged Specification, version 20211203 <https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view>`_. |
7 | 7 |
|
8 | 8 | When entering an interrupt/exception handler, the core sets the ``mepc`` CSR to the current program counter and saves ``mstatus``.MIE to ``mstatus``.MPIE. |
9 | 9 | All exceptions cause the core to jump to the base address of the vector table in the ``mtvec`` CSR. |
@@ -171,13 +171,29 @@ Interrupt vector table |
171 | 171 | ---------------------- |
172 | 172 |
|
173 | 173 | The interrupt vector table is located at ``mtvec``, and each entry can contain the code for |
174 | | -the interrupt/exception handling. The following table indicates the offset of the entry and |
| 174 | +the interrupt/exception handling. |
| 175 | + |
| 176 | + |
| 177 | + When MODE=Direct, all traps into machine mode cause the pc to be set to the address in the BASE field. |
| 178 | + |
| 179 | + When MODE=Vectored, |
| 180 | + |
| 181 | + all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE |
| 182 | + field, |
| 183 | + |
| 184 | + whereas interrupts cause the pc to be set to the address in the BASE field plus four times the |
| 185 | + interrupt cause number. |
| 186 | + |
| 187 | + |
| 188 | +From `RISC-V Privileged Specification, version 20211203, page 30 <https://drive.google.com/file/d/1EMip5dZlnypTk7pt4WWUKmtjUKTOkBqh/view>`_. |
| 189 | + |
| 190 | +The following table indicates the offset of the entry and |
175 | 191 | its description. |
176 | 192 |
|
177 | 193 | +-------------------------+------------------------------------------------------------+ |
178 | 194 | | offset in bytes | Description | |
179 | 195 | +=========================+============================================================+ |
180 | | -| 0x00 | Boot | |
| 196 | +| 0x00 | Exception | |
181 | 197 | +-------------------------+------------------------------------------------------------+ |
182 | 198 | | 0x04 | reserved | |
183 | 199 | +-------------------------+------------------------------------------------------------+ |
|
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