Only read DIMMs in A0HP (#2287)

This includes a workaround for
oxidecomputer/quartz#434; 

and has FPGA fixes for oxidecomputer/quartz#437 and oxidecomputer/quartz#435 which resulted in topo not showing the correct number of dimms or the correct information for the dimms.

I've cycled this ~100 boots without seeing any dimm training failures  so this seems to be reliable.
---------

Co-authored-by: Nathanael Huffman <[email protected]>

Author: mkeeter

drv/spartan7-loader/cosmo-seq/README.md

@@ -1,3 +1,3 @@
 FPGA images and collateral are generated from:
-[this sha](https://github.com/oxidecomputer/quartz/commit/cc132979ecf494ada44c99d614719d68784a0d49)
-[release](https://api.github.com/repos/oxidecomputer/quartz/releases/259632098)
+[this sha](https://github.com/oxidecomputer/quartz/commit/aa85c8b6c59f92fdc05537c7e0a9b30c757f11ce)
+[release](https://api.github.com/repos/oxidecomputer/quartz/releases/263091469)

drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2

@@ -1147,13 +1147,24 @@
                 },
                 {
                     "type": "field",
-                    "inst_name": "v0p96_nic_vdd_a0hp",
+                    "inst_name": "v1p4_nic_a0hp",
                     "lsb": 17,
                     "msb": 17,
                     "reset": null,
                     "sw_access": "rw",
                     "se_onread": null,
                     "se_onwrite": null,
+                    "desc": "NIC v1p4_nic_a0hp (discrete pg, enable cascade from nic 5V). Note: mirrors enable on HCV A boards, actual pin readback on HCV B and newer boards"
+                },
+                {
+                    "type": "field",
+                    "inst_name": "v0p96_nic_vdd_a0hp",
+                    "lsb": 18,
+                    "msb": 18,
+                    "reset": null,
+                    "sw_access": "rw",
+                    "se_onread": null,
+                    "se_onwrite": null,
                     "desc": "NIC v0p96_nic_vdd_a0hp (discrete pg, enable cascade from nic 5V)"
                 }
             ]
@@ -1354,13 +1365,24 @@
                 },
                 {
                     "type": "field",
-                    "inst_name": "v0p96_nic_vdd_a0hp",
+                    "inst_name": "v1p4_nic_a0hp",
                     "lsb": 17,
                     "msb": 17,
                     "reset": null,
                     "sw_access": "r",
                     "se_onread": null,
                     "se_onwrite": null,
+                    "desc": "NIC v1p4_nic_a0hp (discrete pg, enable cascade from nic 5V). Note: mirrors enable on HCV A boards, actual pin readback on HCV B and newer boards"
+                },
+                {
+                    "type": "field",
+                    "inst_name": "v0p96_nic_vdd_a0hp",
+                    "lsb": 18,
+                    "msb": 18,
+                    "reset": null,
+                    "sw_access": "r",
+                    "se_onread": null,
+                    "se_onwrite": null,
                     "desc": "NIC v0p96_nic_vdd_a0hp (discrete pg, enable cascade from nic 5V)"
                 }
             ]
@@ -1561,13 +1583,24 @@
                 },
                 {
                     "type": "field",
-                    "inst_name": "v0p96_nic_vdd_a0hp",
+                    "inst_name": "v1p4_nic_a0hp",
                     "lsb": 17,
                     "msb": 17,
                     "reset": null,
                     "sw_access": "rw",
                     "se_onread": null,
                     "se_onwrite": null,
+                    "desc": "NIC v1p4_nic_a0hp (discrete pg, enable cascade from nic 5V). Note: mirrors enable on HCV A boards, actual pin readback on HCV B and newer boards"
+                },
+                {
+                    "type": "field",
+                    "inst_name": "v0p96_nic_vdd_a0hp",
+                    "lsb": 18,
+                    "msb": 18,
+                    "reset": null,
+                    "sw_access": "rw",
+                    "se_onread": null,
+                    "se_onwrite": null,
                     "desc": "NIC v0p96_nic_vdd_a0hp (discrete pg, enable cascade from nic 5V)"
                 }
             ]

drv/spartan7-loader/cosmo-seq/sequencer_regs.json

@@ -85,12 +85,16 @@ impl ServerImpl {
         // This laborious list is intended to ensure that new power states
         // have to be added explicitly here.
         match PowerState::from_u32(self.jefe.get_state()) {
-            Some(PowerState::A0) | Some(PowerState::A0PlusHP) => {
+            // DIMMS are powered in A0, but we don't want to read them while the
+            // PSP is also reading them, because we can get in fights with its
+            // DIMM training (see quartz#434)
+            Some(PowerState::A0PlusHP) => {
                 if !self.active {
                     self.activate()
                 }
             }
-            Some(PowerState::A2)
+            Some(PowerState::A0)
+            | Some(PowerState::A2)
             | Some(PowerState::A2PlusFans)
             | Some(PowerState::A0Reset)
             | Some(PowerState::A0Thermtrip)