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1 parent c28536f commit 6fd7721Copy full SHA for 6fd7721
pymtl3/passes/backends/verilog/import_/verilator_wrapper_py_template.py
@@ -125,9 +125,9 @@ def __del__( s ):
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def construct( s, *args, **kwargs ):
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# Set up the VCD file name
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verilator_vcd_file = ""
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- if s.has_metadata( VerilogVerilatorImportPass.vl_trace ):
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- if s.has_metadata( VerilogVerilatorImportPass.vl_trace_filename ):
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- verilator_vcd_file = f"{{s.has_metadata(VerilogVerilatorImportPass.vl_trace_filename)}}.verilator1.vcd"
+ if int(s._ip_cfg.vl_trace):
+ if bool(s._ip_cfg.vl_trace_filename):
+ verilator_vcd_file = f"{{s._ip_cfg.vl_trace_filename}}.verilator1.vcd"
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else:
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verilator_vcd_file = "{component_name}.verilator1.vcd"
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