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1 parent 8fda8c0 commit d20ec4dCopy full SHA for d20ec4d
pymtl3/passes/backends/verilog/tbgen/verilog_tbgen_v_template.py
@@ -18,6 +18,8 @@
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`timescale 1ns/1ns
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+`define STRINGIFY(x) `"x`"
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+
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`define T({args_strs}) \\
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t({args_strs},`__LINE__)
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@@ -86,7 +88,7 @@
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always @(negedge {saif_roi_signal} ) begin
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if ( !reset ) begin
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$toggle_stop;
- $toggle_report( "`VTB_DUMP_SAIF", 1e-12, DUT );
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+ $toggle_report( `STRINGIFY(`VTB_DUMP_SAIF), 1e-12, DUT );
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end
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`endif
@@ -146,7 +148,7 @@
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`ifdef VTB_DUMP_SAIF
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`ifndef VTB_DUMP_SAIF_ROI
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