Consider full_case and parallel_case

[tcr]

These are markers used in Verilog to force a type of FSM generation. These are needed if we can guarantee we generate the appropriate FSM types, but it may help to have the extra annotation (especially if we can detect when we generate invalid Verilog cases).

See more about this topic: http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf