[pull] master from YosysHQ:master #258

pull · 2021-04-25T16:33:09Z

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todo · 2021-05-07T10:24:13Z

for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed

Lines 161 to 166 in 432b9d8

    
           // TODO: for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed 
        
           // before the GBs it drives 
        
           for (auto cell : sorted(ctx->cells)) { 
        
               CellInfo *ci = cell.second; 
        
               const GlobalCellPOD *glb_cell = global_cell_info(ci->type); 
        
               if (glb_cell == nullptr)

This comment was generated by todo based on a `TODO` comment in `432b9d8` in #258. cc @YosysHQ.

todo · 2021-05-07T10:24:16Z

substantial performance improvements are probably possible, although of questionable benefit given

nextpnr/fpga_interchange/globals.cc

Lines 200 to 205 in 432b9d8

    
           // TODO: substantial performance improvements are probably possible, although of questionable benefit given 
        
           // the low number of globals in a typical device... 
        
           BelId best_bel; 
        
           int shortest_distance = std::numeric_limits<int>::max(); 
        
           for (auto bel : getBels()) {

This comment was generated by todo based on a `TODO` comment in `432b9d8` in #258. cc @YosysHQ.

Signed-off-by: gatecat <[email protected]>

… XDC file

…DC commands

…r better interoperability with other synthesis tools and RTL languages

* Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks. And the style edits - they get automatically when I make sure to run clang-format10. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

…1381)

* apicula: add support for magic sip pins * fix nullptr check * DDR fix by xiwang * WIP support for setting the iostd * add iostd

Signed-off-by: gatecat <[email protected]>

* Gowin. FFs placement. * Allow clusters to be created from FFs and LUTs; * Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs; * In case of constant networks, such pass-through LUTs are disconnected from networks altogether; * Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix aux name creation Signed-off-by: YRabbit <[email protected]> * Gowin. Use I3 for pass-trough LUTs Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

Over time, it became clear that the special status of corner tiles is handled in other parts of the toolchain, and in the GW5A chip series, it began to interfere—in this series, IO can be located in the corners. So we move the only function (creating VCC and GND) to the extra function itself, and at the same time create a mechanism for explicitly specifying the location of these sources in Apicula when necessary. Signed-off-by: YRabbit <[email protected]>

In the new series of chips, the SemiDual Port primitive has one RESET pin instead of two in previous versions - RESETA and RESETB. Physically, the two pins are still there and both must be connected, with RESETA being constant. Signed-off-by: YRabbit <[email protected]>

If the chipdb is not found, the Setup() call throws, but GTest still calls TearDown, which then stumbles over the uninitialized pointer. This makes the tests fail without valgrind errors or segfaults at least.

…parated by a comma (#1571)

* rust: formatting cleanup * rust: explicitly mark as ISC license * rust: use std::ffi C types instead of libc dependency

In the GW5A series, the primitive SemiDual Port BSRAM cannot function when the width of any of the ports is 32/36 bits - it is necessary to divide one block into two identical ones, each of which will be responsible for 16 bits. Here, we perform such a division and, in addition, ensure that the new cells resulting from the division undergo the same packing procedure as the original ones. Naturally, with some reservations (the AUX attribute is responsible for this) - in the case of SP, when service elements are added, it makes sense to do this immediately for 32-bit SP and only then divide. Also, SDPs are currently being corrected for cases where both ports are ‘problematic’, but it may happen that one port is 32 and the other is, say, 1/2/4/8/16. This has been left for the future. Signed-off-by: YRabbit <[email protected]>

* Use QtPropertyBrowser for Qt5/6 * Fix cmake for python-console for consistency * Make GUI compile for both Qt5 and Qt6 * Fix crash on init with Wayland on Qt6 * Cleanup * disable deprecation warnings for now * Relaxed cmake check for initial Qt6 test

* gatemate: support multiple clock distribution strategies * error out on non supported cases * Implement full use strategy * Address review comments

* gatemate: document clock distribution strategies * gatemate: rename option to strategy

Co-authored-by: OpenProgger <[email protected]>

* remove copy of googletest from 3rdparty * Add googletest as submodule * Use googletest v1.17.0 * Update main CMakeLists.txt

Paired with YosysHQ/yosys@6535995 now that we may receive unattached OBUFs, we ignore them. Signed-off-by: YRabbit <[email protected]>

* gatemate: Use GATEMATE_DIE attribute to select placement die * add DIE parameter in CCF * add penalty delay when crossing between dies * Add predictDelay

* himbaechel: add uarch specific options parsing * fix tests * add reference to additional help * review comments addressed * cleanup and unify other uarch * Adressed PR comments

Signed-off-by: gatecat <[email protected]>

Since ctx->getArchArgs() no longer returns architecture-specific arguments, we read the args field directly. Signed-off-by: YRabbit <[email protected]>

* Cleanup Context API * Remove exit to prvent crash

* gatemate: handle default parameters for IO This is probably a VHDL specific issue. In VHDL, there is no black-box. Primitive instantiations are done using VHDL component instantiations and the component must have been declared with all its ports and parameters (generic). Currently the components are translated from cells_sim.v and cells_bb.v If a user doesn't override a parameter, the default value is used instead. As a consequence, nextpnr can have 'UNDEFINED' for DRIVER or SLEW parameters of CC_IOBUF. I think this is a main difference with verilog, where unspecified parameters do not appear. With this change, the UNPLACED value of PIN_NAME and UNDEFINED value of DRIVE are simply ignored. * gatemate/pack_io.cc: also handle UNDEFINED for id_SLEW

ADC support for GW5A-25 chips has been added. The inputs of this primitive are fixed and do not require routing, although they can be switched dynamically. The .CST file also specifies the pins used as signal sources for the bus0 and bus1 ADC buses. Signed-off-by: YRabbit <[email protected]>

The TLVDS_IBUF_ADC IO primitives have been implemented, which provide a signal for ADC bus 2. These differential IO primitives also have an additional input that allows them to be disabled, thereby providing dynamic switching of the signal source for the ADC. Signed-off-by: YRabbit <[email protected]>

* small cleanup * gatemate: pack output flops for multipliers * remove possibly-inaccurate comments

pull bot added the ⤵️ pull label Apr 25, 2021

gatecat and others added 27 commits September 26, 2024 15:56

xilinx: Filter out another missing pip type

c90d872

Signed-off-by: gatecat <[email protected]>

xilinx: Remove unnecessary assert

118ecbc

Signed-off-by: gatecat <[email protected]>

xilinx: Few more stub timings

7516b89

Signed-off-by: gatecat <[email protected]>

xilinx: Support single-port LUTRAM variants

e4dfd4e

Signed-off-by: gatecat <[email protected]>

xilinx: Fix workaround for unsupported xdc construct

38e5fac

Signed-off-by: gatecat <[email protected]>

xilinx: Fix BRAM placement, clangformat

d3c0f94

Signed-off-by: gatecat <[email protected]>

xilinx: Basic I/ODDR support

24fc33c

Signed-off-by: gatecat <[email protected]>

xilinx: Support for complex IOLOGIC

1967db1

Signed-off-by: gatecat <[email protected]>

Remove fpga_interchange

fcdaf3f

Signed-off-by: gatecat <[email protected]>

clangformat

9b51c6e

Signed-off-by: gatecat <[email protected]>

BaseCtx : Fix crash in getNetByAlias()

cc04882

Himbaechel Xilinx : More warning messages about unsupported things in…

ff9ba9e

… XDC file

Himbaechel Xilinx : Support multiple nets per command

a9cc7f4

Himbaechel Xilinx : Support get_nets with braces around net name in X…

3d00b97

…DC commands

Himbaechel Xilinx : XDC commands : Also search nets with lowercase fo…

7f33329

…r better interoperability with other synthesis tools and RTL languages

clang-format on basectx.h

b3b2392

router2: additional heatmap data

268b32c

heap: Fix ripup criterea (#1378)

75d2ce6

Signed-off-by: gatecat <[email protected]>

ice40: Fix missing clock pin types (#1380)

854549a

Signed-off-by: gatecat <[email protected]>

timing_log: Handle potentially missing net when reporting crit path (#…

0e5b134

…1381)

Placer: Fix static legalise radius (#1382)

d27993f

apicula: add support for magic sip pins (#1370)

028be14

* apicula: add support for magic sip pins * fix nullptr check * DDR fix by xiwang * WIP support for setting the iostd * add iostd

himbaechel: Bump DB version for package extra_data addition

7c45980

Signed-off-by: gatecat <[email protected]>

Fix RNG seed initialization (#1383)

cf42baa

cmake: Use upstream BoostConfig.cmake instead of cmake's own (#1387)

f36a657

Signed-off-by: gatecat <[email protected]>

mmicko and others added 30 commits September 30, 2025 14:20

clangformat

e16bd45

gatemate: respect keep attribute and prevent crash with BEL set (#1566)

ad76625

placer_heap: fix clamping to region (#1569)

e7f9060

ice40: Initialize context pointer in tests (#1568)

5d45520

If the chipdb is not found, the Setup() call throws, but GTest still calls TearDown, which then stumbles over the uninitialized pointer. This makes the tests fail without valgrind errors or segfaults at least.

himbaechel/uarch/gowin/cst.cc: added support for IO_LOC with _p/_n se…

4b00f58

…parated by a comma (#1571)

Rust cleanup (#1573)

35810c9

* rust: formatting cleanup * rust: explicitly mark as ISC license * rust: use std::ffi C types instead of libc dependency

MachXO2. Add support for several IO parameters. (#1572)

5194b5c

gatemate: support multiple clock distribution strategies (#1574)

3604554

* gatemate: support multiple clock distribution strategies * error out on non supported cases * Implement full use strategy * Address review comments

clangformat

f245185

gatemate: document clock distribution strategies (#1580)

f19a671

* gatemate: document clock distribution strategies * gatemate: rename option to strategy

gatemate: bump chipdb to 1.9

9d7e1d0

Update CI and README for Qt6 (#1584)

6d187fb

Co-authored-by: OpenProgger <[email protected]>

Google Test as submodule (#1579)

64db93e

* remove copy of googletest from 3rdparty * Add googletest as submodule * Use googletest v1.17.0 * Update main CMakeLists.txt

Gowin. Delete unused OBUFs. (#1581)

dfef396

Paired with YosysHQ/yosys@6535995 now that we may receive unattached OBUFs, we ignore them. Signed-off-by: YRabbit <[email protected]>

gatemate: properly name timing and operational mode (#1587)

924f3a5

gatemate: additional region handling (#1583)

c6f408d

* gatemate: Use GATEMATE_DIE attribute to select placement die * add DIE parameter in CCF * add penalty delay when crossing between dies * Add predictDelay

himbaechel: add uarch specific options parsing (#1582)

9ccd132

* himbaechel: add uarch specific options parsing * fix tests * add reference to additional help * review comments addressed * cleanup and unify other uarch * Adressed PR comments

Remove use of boost system and filesystem (#1591)

c7cfb0a

Signed-off-by: gatecat <[email protected]>

Gowin. Take the arch arguments directly. (#1592)

c133d00

Since ctx->getArchArgs() no longer returns architecture-specific arguments, we read the args field directly. Signed-off-by: YRabbit <[email protected]>

Cleanup Context API (#1593)

a530283

* Cleanup Context API * Remove exit to prvent crash

gatemate: fix SERDES CDR parameters (#1596)

30669ec

Bump gatemate chip database

69facd7

gatemate: pack multiplier output registers (#1603)

cfa5f77

* small cleanup * gatemate: pack output flops for multipliers * remove possibly-inaccurate comments

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[pull] master from YosysHQ:master #258

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pull bot commented Apr 25, 2021 •

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todo bot commented May 7, 2021

for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed

This comment was generated by todo based on a TODO comment in 432b9d8 in #258. cc @YosysHQ.

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todo bot commented May 7, 2021

substantial performance improvements are probably possible, although of questionable benefit given

This comment was generated by todo based on a TODO comment in 432b9d8 in #258. cc @YosysHQ.

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pull bot commented Apr 25, 2021 •

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This comment was generated by todo based on a `TODO` comment in `432b9d8` in #258. cc @YosysHQ.

This comment was generated by todo based on a `TODO` comment in `432b9d8` in #258. cc @YosysHQ.