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Expand file tree Collapse file tree 3 files changed +307
-131
lines changed Original file line number Diff line number Diff line change @@ -97,11 +97,24 @@ func main() {
9797 // After configuring PLLs and clocks, enable the outputs.
9898 clockgen .EnableOutputs ()
9999
100+ time .Sleep (time .Second )
101+
102+ clockgen .DisableOutputs ()
103+ println ("All outputs disabled for 5 seconds" )
104+ time .Sleep (5 * time .Second )
105+
106+ // Now use SetFrequency to re-set the frequencies of the outputs
107+ on := false
100108 for {
109+ if on {
110+ println ("Setting Clock 0 output off" )
111+ clockgen .OutputEnable (0 , false )
112+ on = false
113+ } else {
114+ println ("Setting Clock 0 output to 100mhz" )
115+ clockgen .SetFrequency (100 * machine .MHz , 0 , si5351 .PLL_A )
116+ on = true
117+ }
101118 time .Sleep (5 * time .Second )
102- println ()
103- println ("Clock 0: 112.5mhz" )
104- println ("Clock 1: 13.5531mhz" )
105- println ("Clock 2: 10.706khz" )
106119 }
107120}
Original file line number Diff line number Diff line change @@ -62,3 +62,18 @@ const (
6262 MULTISYNTH_DIV_6 = 6
6363 MULTISYNTH_DIV_8 = 8
6464)
65+
66+ // Frequency constants (in Hz)
67+ const (
68+ CLKOUT_MIN_FREQ = 8000 // 8 kHz
69+ CLKOUT_MAX_FREQ = 150000000 // 150 MHz
70+ MULTISYNTH_MAX_FREQ = 150000000 // 150 MHz
71+ MULTISYNTH_SHARE_MAX = 100000000 // 100 MHz
72+ MULTISYNTH_DIVBY4_FREQ = 150000000 // 150 MHz
73+ PLL_VCO_MIN = 600000000 // 600 MHz
74+ PLL_VCO_MAX = 900000000 // 900 MHz
75+ )
76+
77+ const (
78+ SI5351_PLL_C_MAX = 1048575
79+ )
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