Update documents

Author: tomoasleep

LICENSE

@@ -1,4 +1,4 @@
-Copyright (c) 2012 tomykaira
+Copyright (c) 2013 Tomoya Chiba, tomykaira
 
 MIT License
 
@@ -19,4 +19,4 @@ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

README.md

@@ -1,6 +1,7 @@
 # VhdlTestScript
 
-This is DSL with Ruby to create VHDL test bench easily and test runner. (This Project is forked from [tomykaira/vhdl_doctest](https://github.com/tomykaira/vhdl_doctest))
+VhdlTestScript is a test-driven development Tool for VHDL  
+(This Project is forked from [tomykaira/vhdl_doctest](https://github.com/tomykaira/vhdl_doctest))
 
 ## Dependency
 
@@ -14,9 +15,45 @@ This uses GHDL for compiling and running VHDL.  Please download from [GHDL Main/
 
 Install GHDL from [GHDL Main/Home Page](http://ghdl.free.fr).
 
+## Usage
+
+To use VhdlTestScript, you write test benches with ruby like this.
+
+```ruby
+VhdlTestScript.scenario DUT_PATH do |dut|
+  # please write your test scenario here
+
+  # Example:
+  # 'a' is 'in' port , 'output' is 'out' port.
+  # declare port to use test as ':a' or 'dut.a'
+  ports :a, :output
+
+  # to use 'in' port 'clk' as clock.
+  clock :clk
+
+  # when 'a' is assigned '1' before rising edge,
+  # 'output' is expected to be '1' after clock.
+  step 1, 1
+
+  step 2, 2
+
+  # '_' means 'don't assign' or 'don't care'.
+  step _, 2
+  step 1, _
+
+  # you can use 'step' like this
+  step a: 1, output: 1
+end
+```
+
+this ruby test bench is converted into a VHDL test bench when run vhdltestscript
+
+Documentation of test scenario syntax is being developed now.
+Please read example codes in /example to know how to write test scenario.
+
 ## Issues And Features
 
-If you found a bug (or unexpected movement), let me know.  Please attach your vhd file (as far as possible), and describe your intention precisely.
+If you found a bug (or unexpected movement), let me know.  Please attach your vhd and test bench file (as far as possible), and describe your intention precisely.
 
 Any feature request is welcome.  I appreciate if it have an example, or a test case.