address comments

Author: Wolfram70

llvm/include/llvm/IR/IntrinsicsNVVM.td

@@ -1378,16 +1378,16 @@ let TargetPrefix = "nvvm" in {
 
   foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
     foreach ftz = ["", "_ftz"] in {
-      foreach sat = ["", "_sat"] in
+      foreach sat = ["", "_sat"] in {
         def int_nvvm_fma # rnd # ftz # sat # _f : NVVMBuiltin,
           PureIntrinsic<[llvm_float_ty],
             [llvm_float_ty, llvm_float_ty, llvm_float_ty]>;
-    }
-
+      } // sat
+    } // ftz
     def int_nvvm_fma # rnd # _d : NVVMBuiltin,
       PureIntrinsic<[llvm_double_ty],
         [llvm_double_ty, llvm_double_ty, llvm_double_ty]>;
-  }
+  } // rnd
 
   //
   // Rcp
@@ -1447,14 +1447,14 @@ let TargetPrefix = "nvvm" in {
   let IntrProperties = [IntrNoMem, IntrSpeculatable, Commutative] in {
     foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
       foreach ftz = ["", "_ftz"] in {
-        foreach sat = ["", "_sat"] in
+        foreach sat = ["", "_sat"] in {
           def int_nvvm_add # rnd # ftz # sat # _f : NVVMBuiltin,
             DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty]>;
-      }
-
+        } // sat
+      } // ftz
       def int_nvvm_add # rnd # _d : NVVMBuiltin,
           DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty]>;
-    }
+    } // rnd
   }
 
   //
@@ -1463,14 +1463,14 @@ let TargetPrefix = "nvvm" in {
   let IntrProperties = [IntrNoMem, IntrSpeculatable] in {
     foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
       foreach ftz = ["", "_ftz"] in {
-        foreach sat = ["", "_sat"] in
+        foreach sat = ["", "_sat"] in {
           def int_nvvm_sub # rnd # ftz # sat # _f : NVVMBuiltin,
           DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty]>;
-      }
-
+        } // sat
+      } // ftz
       def int_nvvm_sub # rnd # _d : NVVMBuiltin,
           DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty]>;
-    }
+    } // rnd
   }
 
   //

llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

@@ -1702,16 +1702,16 @@ multiclass FMA_INST {
 
 defm INT_NVVM_FMA : FMA_INST;
 
-foreach rnd = ["_RN", "_RZ", "_RM", "_RP"] in {
-  foreach sat = ["", "_SAT"] in {
-    foreach type = ["F16", "BF16"] in {
-      def INT_NVVM_FMA # rnd # sat # _F32_ # type : 
+foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
+  foreach sat = ["", "_sat"] in {
+    foreach type = ["f16", "bf16"] in {
+      def INT_NVVM_MIXED_FMA # rnd # sat # _f32_ # type : 
         BasicNVPTXInst<(outs B32:$dst), (ins B16:$a, B16:$b, B32:$c),
-          !tolower(!subst("_", ".", "fma" # rnd # sat # "_f32_" # type)),
+          !subst("_", ".", "fma" # rnd # sat # "_f32_" # type),
           [(set f32:$dst, 
-           (!cast<Intrinsic>(!tolower("int_nvvm_fma" # rnd # sat # "_f")) 
-             (f32 (fpextend !cast<ValueType>(!tolower(type)):$a)),
-             (f32 (fpextend !cast<ValueType>(!tolower(type)):$b)),
+           (!cast<Intrinsic>("int_nvvm_fma" # rnd # sat # "_f") 
+             (f32 (fpextend !cast<ValueType>(type):$a)),
+             (f32 (fpextend !cast<ValueType>(type):$b)),
              f32:$c))]>,
         Requires<[hasSM<100>, hasPTX<86>]>;
     }
@@ -1838,15 +1838,15 @@ def INT_NVVM_ADD_RZ_D : F_MATH_2<"add.rz.f64", B64, B64, B64, int_nvvm_add_rz_d>
 def INT_NVVM_ADD_RM_D : F_MATH_2<"add.rm.f64", B64, B64, B64, int_nvvm_add_rm_d>;
 def INT_NVVM_ADD_RP_D : F_MATH_2<"add.rp.f64", B64, B64, B64, int_nvvm_add_rp_d>;
 
-foreach rnd = ["_RN", "_RZ", "_RM", "_RP"] in {
-  foreach sat = ["", "_SAT"] in {
-    foreach type = ["F16", "BF16"] in {
-      def INT_NVVM_ADD # rnd # sat # _F32_ # type : 
+foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
+  foreach sat = ["", "_sat"] in {
+    foreach type = ["f16", "bf16"] in {
+      def INT_NVVM_MIXED_ADD # rnd # sat # _f32_ # type : 
         BasicNVPTXInst<(outs B32:$dst), (ins B16:$a, B32:$b),
-          !tolower(!subst("_", ".", "add" # rnd # sat # "_f32_" # type)),
+          !subst("_", ".", "add" # rnd # sat # "_f32_" # type),
           [(set f32:$dst, 
-           (!cast<Intrinsic>(!tolower("int_nvvm_add" # rnd # sat # "_f")) 
-             (f32 (fpextend !cast<ValueType>(!tolower(type)):$a)),
+           (!cast<Intrinsic>("int_nvvm_add" # rnd # sat # "_f") 
+             (f32 (fpextend !cast<ValueType>(type):$a)),
              f32:$b))]>,
         Requires<[hasSM<100>, hasPTX<86>]>;
     }
@@ -1878,15 +1878,15 @@ def INT_NVVM_SUB_RZ_D : F_MATH_2<"sub.rz.f64", B64, B64, B64, int_nvvm_sub_rz_d>
 def INT_NVVM_SUB_RM_D : F_MATH_2<"sub.rm.f64", B64, B64, B64, int_nvvm_sub_rm_d>;
 def INT_NVVM_SUB_RP_D : F_MATH_2<"sub.rp.f64", B64, B64, B64, int_nvvm_sub_rp_d>;
 
-foreach rnd = ["_RN", "_RZ", "_RM", "_RP"] in {
-  foreach sat = ["", "_SAT"] in {
-    foreach type = ["F16", "BF16"] in {
-      def INT_NVVM_SUB # rnd # sat # _F32_ # type : 
+foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
+  foreach sat = ["", "_sat"] in {
+    foreach type = ["f16", "bf16"] in {
+      def INT_NVVM_MIXED_SUB # rnd # sat # _f32_ # type : 
         BasicNVPTXInst<(outs B32:$dst), (ins B16:$a, B32:$b),
-          !tolower(!subst("_", ".", "sub" # rnd # sat # "_f32_" # type)),
+          !subst("_", ".", "sub" # rnd # sat # "_f32_" # type),
           [(set f32:$dst, 
-           (!cast<Intrinsic>(!tolower("int_nvvm_sub" # rnd # sat # "_f")) 
-             (f32 (fpextend !cast<ValueType>(!tolower(type)):$a)),
+           (!cast<Intrinsic>("int_nvvm_sub" # rnd # sat # "_f") 
+             (f32 (fpextend !cast<ValueType>(type):$a)),
              f32:$b))]>,
         Requires<[hasSM<100>, hasPTX<86>]>;
     }