Add tohost capabilities to corev-dv

Mario · Mario · commit 9fd99344eed2 · 2023-10-03T07:47:27.000Z
lib/corev-dv/corev_asm_program_gen.sv: delete wfi and add syscall on
ecall
cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_*: change
align of trap handler to 8
diff --git a/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S b/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S
@@ -2,7 +2,7 @@
 #.include "user_define.h"
 #.globl _start
 #.section .text
-#_start:           
+#_start:
 # END: riscv-dv
 # BEGIN: gtumbush
 .include "user_define.h"
@@ -18,7 +18,7 @@ _start:
 
 .globl _start_main
 .section .text
-_start_main:          
+_start_main:
 # END: gtumbush
 # BEGIN: riscv-dv
                   csrr x5, mhartid
@@ -29,20 +29,20 @@ _start_main:
 h0_start:
                   li x30, 0x40001104
                   csrw misa, x30
-kernel_sp:        
+kernel_sp:
                   la x13, kernel_stack_end
 
-trap_vec_init:    
+trap_vec_init:
                   la x30, mtvec_handler
                   ori x30, x30, 1
                   csrw 0x305, x30 # MTVEC
 
-mepc_setup:       
+mepc_setup:
                   la x30, init
                   csrw mepc, x30
                   j init_machine_mode
 
-init:             
+init:
                   li x0, 0xffae545d
                   li x1, 0xf
                   li x2, 0xfaea503e
@@ -11309,17 +11309,14 @@ fast_exit:
                   lw a1, test_results /* report result */
                   sw a1,0(a0)
 
-                  wfi  /* we are done */
-##End: Extracted from riscv_compliance_tests/riscv_test.h
-
                   j test_done
-test_done:        
+test_done:
                   li gp, 1
                   ecall
-write_tohost:     
+write_tohost:
                   sw gp, tohost, t5
 
-_exit:            
+_exit:
                   j write_tohost
 
 init_machine_mode:
@@ -11328,7 +11325,7 @@ init_machine_mode:
                   li x30, 0x0
                   csrw 0x304, x30 # MIE
                   mret
-instr_end:        
+instr_end:
                   nop
 
 .section .data
@@ -11960,8 +11957,8 @@ mmode_intr_vector_15:
                   j mmode_intr_handler
                   1: j test_done
 
-.align 2
-mtvec_handler:    
+.align 8
+mtvec_handler:
                   .option norvc;
                   j mmode_exception_handler
                   j mmode_intr_vector_1
@@ -12041,9 +12038,9 @@ mmode_exception_handler:
                   li x22, 0x2 # ILLEGAL_INSTRUCTION
                   beq x30, x22, illegal_instr_handler
                   csrr x22, 0x343 # MTVAL
-                  1: jal x1, test_done 
+                  1: jal x1, test_done
 
-ecall_handler:    
+ecall_handler:
                   la x30, _start
                   sw x0, 0(x30)
                   sw x1, 4(x30)
@@ -12189,7 +12186,7 @@ store_fault_handler:
                   csrrw x12, 0x340, x12
                   mret
 
-ebreak_handler:   
+ebreak_handler:
                   csrr  x30, mepc
                   addi  x30, x30, 4
                   csrw  mepc, x30
@@ -12269,7 +12266,7 @@ illegal_instr_handler:
                   csrrw x12, 0x340, x12
                   mret
 
-pt_fault_handler: 
+pt_fault_handler:
                   nop
 
 .align 2
diff --git a/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S b/cv32e20/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S
@@ -2,7 +2,7 @@
 #.include "user_define.h"
 #.globl _start
 #.section .text
-#_start:           
+#_start:
 # END: riscv-dv
 # BEGIN: gtumbush
 .include "user_define.h"
@@ -17,7 +17,7 @@ _start:
 
 .globl _start_main
 .section .text
-_start_main:          
+_start_main:
 # END: gtumbush
 # BEGIN: riscv-dv
                   csrr x5, mhartid
@@ -28,20 +28,20 @@ _start_main:
 h0_start:
                   li x10, 0x40001104
                   csrw misa, x10
-kernel_sp:        
+kernel_sp:
                   la x31, kernel_stack_end
 
-trap_vec_init:    
+trap_vec_init:
                   la x10, mtvec_handler
                   ori x10, x10, 1
                   csrw 0x305, x10 # MTVEC
 
-mepc_setup:       
+mepc_setup:
                   la x10, init
                   csrw mepc, x10
                   j init_machine_mode
 
-init:             
+init:
                   li x0, 0xfd790eda
                   li x1, 0x80000000
                   li x2, 0x6
@@ -11355,16 +11355,13 @@ fast_exit:
                   lw a1, test_results /* report result */
                   sw a1,0(a0)
 
-                  wfi  /* we are done */
-##End: Extracted from riscv_compliance_tests/riscv_test.h
-
-test_done:        
+test_done:
                   li gp, 1
                   ecall
-write_tohost:     
+write_tohost:
                   sw gp, tohost, t5
 
-_exit:            
+_exit:
                   j write_tohost
 
 init_machine_mode:
@@ -11373,7 +11370,7 @@ init_machine_mode:
                   li x10, 0x0
                   csrw 0x304, x10 # MIE
                   mret
-instr_end:        
+instr_end:
                   nop
 
 .section .data
@@ -12005,8 +12002,8 @@ mmode_intr_vector_15:
                   j mmode_intr_handler
                   1: j test_done
 
-.align 2
-mtvec_handler:    
+.align 8
+mtvec_handler:
                   .option norvc;
                   j mmode_exception_handler
                   j mmode_intr_vector_1
@@ -12086,9 +12083,9 @@ mmode_exception_handler:
                   li x2, 0x2 # ILLEGAL_INSTRUCTION
                   beq x10, x2, illegal_instr_handler
                   csrr x2, 0x343 # MTVAL
-                  1: jal x1, test_done 
+                  1: jal x1, test_done
 
-ecall_handler:    
+ecall_handler:
                   la x10, _start
                   sw x0, 0(x10)
                   sw x1, 4(x10)
@@ -12234,7 +12231,7 @@ store_fault_handler:
                   csrrw x15, 0x340, x15
                   mret
 
-ebreak_handler:   
+ebreak_handler:
                   csrr  x10, mepc
                   addi  x10, x10, 4
                   csrw  mepc, x10
@@ -12314,10 +12311,10 @@ illegal_instr_handler:
                   csrrw x15, 0x340, x15
                   mret
 
-pt_fault_handler: 
+pt_fault_handler:
                   nop
 
-.align 2
+.align 8
 mmode_intr_handler:
                   csrr  x10, 0x300 # MSTATUS;
                   csrr  x10, 0x304 # MIE;
diff --git a/lib/corev-dv/corev_asm_program_gen.sv b/lib/corev-dv/corev_asm_program_gen.sv
@@ -118,6 +118,7 @@ class corev_asm_program_gen extends riscv_asm_program_gen;
     if (cfg.bare_program_mode) begin
       instr_stream.push_back({indent, "j write_tohost"});
     end else begin
+      instr_stream.push_back({indent, "addi a0,x0,48"}); // Shutdown syscall
       instr_stream.push_back({indent, "ecall"});
     end
   endfunction : gen_test_done
@@ -132,6 +133,11 @@ class corev_asm_program_gen extends riscv_asm_program_gen;
             $sformatf("csrw  mepc, x%0d", cfg.gpr[0])
     };
     pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr);
+
+    instr.push_back("li t0,48"); // Shutdown syscall
+    instr.push_back("bne a0,t0,1f");
+    instr.push_back("j write_tohost");
+    instr.push_back("1:");
     instr.push_back("mret");
     gen_section(get_label("ecall_handler", hart), instr);
   endfunction : gen_ecall_handler
