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@emgens emgens commented Dec 13, 2023

Added explicit check for non implemented CSR's to riscv_csr test.
Cleaned up cv32e20_csr_template.yaml.
This should run cleanly with cve2 pull request 167
There is an entry to work around issue 179, this should be removed once this issue is cleared.

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@MikeOpenHWGroup MikeOpenHWGroup left a comment

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LGTM @emgens. Really appreciate the README!

Question: when I run riscv_csr locally with Questasim it fails with this error message:

# ERROR: Unexpected illegal instruction while accessing CSR 0xc00

I assume that this is related to #166, is that correct?

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emgens commented Dec 13, 2023

LGTM @emgens. Really appreciate the README!

Question: when I run riscv_csr locally with Questasim it fails with this error message:

# ERROR: Unexpected illegal instruction while accessing CSR 0xc00

I assume that this is related to #166, is that correct?

It's #167, but yes. That pull request implements the user space CSR's, so you'll get this error if that isn't included.

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emgens commented Dec 15, 2023

There are known failures in this test case that should be resolved by CVE2 pull request #167

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Thanks @emgens. I will merge this in and add the riscv_csr test to the CI regression when cve2 #167 is resolved.

@MikeOpenHWGroup MikeOpenHWGroup merged commit 439a0a6 into openhwgroup:cv32e20/dev Dec 15, 2023
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