Add PSRAM half Sleep and DCache support for Siwx91x #155
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Add d_cache sdk files in import_wiseconnect.py Signed-off-by: S Mohamed Fiaz <[email protected]>
Origin: Silicon Labs WiseConnect SDK License: Zlib and Apache-2.0 URL: https://github.com/siliconlabs/wiseconnect Commit: 74254b81a6fb92f5edfdae037ab4b1d110067db5 Version: v3.5.2 Purpose: Add D_Cache support for SiWx91x Signed-off-by: S Mohamed Fiaz <[email protected]>
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Nov 27, 2025
wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h
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wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c
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jerome-pouiller
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Nov 28, 2025
wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h
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| #ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE | ||
| #include "sl_si91x_psram.h" | ||
| #endif |
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Unless the target file does not exist, avoid conditionally include the header files (unused declarations don't hurt the code).
| #error "No valid PSRAM configuration defined" | ||
| #endif | ||
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| #endif |
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Maybe this is the right place for the Zephyr configuration:
- Add the various macro based on the DT in
sl_si91x_psram_zephyr_config.h - Include this file if
__ZEPHYR__is defined:
#if defined(SLI_SI91X_MCU_PSRAM_APS1604M_SQR)
...
#elif __ZEPHYR__
#include "sl_si91x_psram_zephyr_config.h"
#endif
| #error "No valid PSRAM configuration defined" | ||
| #endif | ||
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| #endif |
wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram.h
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Included sl_si91x_psram.h under __ZEPHYR__ guard to ensure compatibility with Zephyr builds. Signed-off-by: S Mohamed Fiaz <[email protected]>
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Applied __ZEPHYR__ guards around PSRAM configuration and related includes to restrict PSRAM-specific code to non-Zephyr builds. Signed-off-by: S Mohamed Fiaz <[email protected]>
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| #include "sl_si91x_psram_aps6404l_sqh_config.h" | ||
| #elif defined(SLI_SI91X_MCU_PSRAM_APS6404L_SQRH) | ||
| #include "sl_si91x_psram_aps6404l_sqrh_config.h" | ||
| #elif __ZEPHYR__ |
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I understand this patch but is there any actions to take in Wiseconnect in order to avoid that stuff in the next release of Wiseconnect ? Remenber that @jerome-pouiller is trying to reduce the number of patch in wiseconnect so each time we introduce a new one, we should think to remove it in the next release.
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let me check through if we can do any in here
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Origin: Silicon Labs WiseConnect SDK
License: Zlib and Apache-2.0
URL: https://github.com/siliconlabs/wiseconnect
Commit: 74254b81a6fb92f5edfdae037ab4b1d110067db5
Version: v3.5.2
Purpose: Add PSRAM half sleep mode support.
This functionality enables low-power operations for
PSRAM half sleep supported devices.
Signed-off-by: S Mohamed Fiaz [email protected]